摘要：With increasing the number of cores on a chip inChip-Multiprocessors (CMPs), more cache resources areneeded, and as a result, the leakage power consumption of thecache accounts for a larger proportion of the total chip powerconsumption. The emerging non-volatile memory (NVM) isexpected to replace traditional memory devices due to its highdensity, near zero leakage power, and nonvolatility. In thispaper, we use STT-RAM, a most promising candidate of NVM,to construct a energy-efficient hybrid cache architecture for 3DCMP. For the hybrid cache architecture design, we proposed aspherical placement approach to determine the optimalplacement of STT-RAM and SRAM cache banks. This paperfurther proposes an optimized hybrid cache dynamic migrationscheme, to reduce the data migration jitter and solve theproblem of data migration failure in the hybrid cachearchitecture. The experimental results show that our proposedhybrid cache architecture with spherical placement andoptimized data migration scheme can achieve 34.94% energysaving on average with only 1.49% performance degradation,compared with the architecture which uses pure SRAM as thecache in the same capacity.
关键词：Chip multiprocessors; data migration; hybrid;cache; non-volatile memory
