期刊名称：International Journal on Electrical Engineering and Informatics
印刷版ISSN：2085-6830
出版年度：2019
卷号：11
期号：2
页码：252-262
DOI：10.15676/ijeei.2019.11.2.2
出版社：School of Electrical Engineering and Informatics
摘要：In this work, eight existing master slave single-edge-triggered flip-flops have beenanalyzed in 130nm process node. A new master slave single-edge-triggered flip-flop has alsobeen proposed. The proposed flip-flop is compared with the existing flip-flops on the basis ofpower consumption, propagation delay and power delay product (PDP). Special emphasis hasbeen given to power consumption. The power performance of all flip-flops as a function ofsupply voltage, clock frequency and data activity has been observed. TSpice results of powerconsumption show that the proposed flip-flop design excels rival designs for all supply voltages;all clock frequencies and all data patterns. Thus the proposed flip-flop is most power efficientflip-flop. This flip-flop also shows the third shortest delay and the second lowest PDP among alldiscussed flip-flops. The proposed flip-flop is best suitable for systems where low power andlow area is of primary interest within a certain timing budget.
关键词：VLSI; Latency; Low power design; Critical path; PDP
