期刊名称：Lecture Notes in Engineering and Computer Science
印刷版ISSN：2078-0958
电子版ISSN：2078-0966
出版年度：2018
卷号：2235&2236
页码：236-240
出版社：Newswood and International Association of Engineers
摘要：As Moore’s law continues, the number of cores on
a chip in Chip-Multiprocessors (CMPs) has been increasing. As
the number of cores increases, more cache resources are needed,
and as a result, the leakage power consumption of the cache
accounts for a larger proportion of the total chip power
consumption. The emerging non-volatile memory (NVM) is
expected to replace traditional memory devices due to its high
density, near zero leakage power, and non-volatile memory. In
this paper, we use STT-RAM, a most promising candidate of
NVM, in the cache architecture. We proposes a hybrid cache
spherical placement scheme for 3D CMP, which reduces power
consumption by 34.94% and performance by only 1.49%
degradation compared to a CMP architecture that uses SRAM
as cache with the same capacity. Based on this hybrid cache
architecture, this paper further studies the problem of hybrid
cache data migration in 3D CMP and proposes a hybrid
multicore cache dynamic migration scheme. This scheme
reduces the data migration jitter of 3D CMP by recording the
previous migration information of data and restricting the data
migration from SRAM to STT-RAM, and solves the problem of
data migration failure of hybrid cache.
