期刊名称：Lecture Notes in Engineering and Computer Science
印刷版ISSN：2078-0958
电子版ISSN：2078-0966
出版年度：2018
卷号：2235&2236
页码：662-666
出版社：Newswood and International Association of Engineers
摘要：The increasing demand for miniaturization and
high function integration in today’s microelectronic industry
poses a big challenge in maintaining the reliability of the
package. Majority of the reliability problems can be attributed
to thermal and mechanical loadings during manufacturing and
assembly process. One of the most common defects originating
from these processes is die tilting. In this study, the behavior of
a Small Outline Transistor (SOT) when exposed to thermal
loads was analyzed using finite element method. This work also
investigated the effect of varying solder tilt angle configurations
on the stresses experienced by the package. A 5-layer, multimaterial,
non-symmetric SOT package was modeled in detail to
determine the interlayer stresses caused upon by the CTE
mismatched between each material. Three different tilt angle
configurations for both upper and bottom solder were
simulated using ANSYS software. The 3D model of the package
was exposed to temperature load of 370˚C and cooled down to
room temperature. Material modeling and mesh sensitivity
analysis were also conducted in this research to determine the
most appropriate material type and mesh density to be used for
the simulation. The maximum principal stress distribution,
taken after the cooling stage of die bonding process, was used as
a criterion to determine the location of the maximum stress on
the silicon die. Results from the simulation have shown that the
maximum principal stress distribution shifted to the area of
thinner solder as the tilt angle is increased. The results holds
true for both upper and bottom solder tilting. In addition, the
results show that the magnitude of the stresses in the area
where the solder becomes the thinnest also increases. This study
presents a clear relationship between the thermo-mechanical
response of the silicon die and changing die tilt angles. These
observations can be helpful in detecting and locating the
possible site of failure and can be used to develop more reliable
microelectronic packages.
关键词：ANSYS; Die Tilt; Small Outline Transistor;;
Thermo-mechanical
