标题：Investigation of the Effect of Varying Silicon Die Size and Thickness on a Small Outline Transistor on the Silicon Die Crack Using Finite Element Method
期刊名称：Lecture Notes in Engineering and Computer Science
印刷版ISSN：2078-0958
电子版ISSN：2078-0966
出版年度：2018
卷号：2235&2236
页码：716-720
出版社：Newswood and International Association of Engineers
摘要：The current trend for electronic products,
especially those in telecommunications, is to be more compact.
To match the demand for compact products, a size reduction
of electronic product components such as the small outline
transistor (SOT) is therefore needed. This work utilized the
finite element method with a fracture mechanics approach to
analyze the effect of varying geometric parameters on the Jintegral
of the existing crack on the silicon die. The J-integral
values obtained generally showed a peak value with the midsized
silicon die. The J-integral value generally decreased with
die thickness but was found to be minimum at around 100 mm
die thickness. A further reduction in thickness resulted in an
increase in J-integral. Results from the simulations will be
helpful in determining the effect of these parameters on the
reliability of the package with respect to die crack risk and can
be utilized to guide improvements on the existing package
design.
关键词：ANSYS; die crack; j-integral; small-outline;
transistor
