摘要：This paper focuses on the carrier disposition Pulse Width Modulation (PWM) strategies for
Modular Multilevel Converters (MMC). The authors propose a new Phase Opposition
Disposition PWM (PODPWM) scheme applicable regardless of the converter’s sub-modules
number. Moreover, a capacitor voltage sorting algorithm is synthesized aiming to ensure the
converter’s balanced operation. Simulation results of a 3.6 MVA, 3-SM-MMC are presented
and discussed. In addition, a Hardware In the Loop (HIL) validation of the proposed
PODPWM has been made using Field Programmable Gate Array (FPGA) target. The actual
power system (the 3-SM-MMC and the 3-phase RL load) is then replaced by its real-time
emulator. The latter is interfaced to the PODPWM control under test and both are
implemented and run altogether in the same Xilinx XC7Z020 Zynq FPGA device. The obtained
real-time HIL emulation results are presented and compared to the offline simulation results.
关键词：Modular multilevel converter; Pulse Width Modulation; circulating current; active;
balance; Real-time Emulator; Hardware In the Loop
