期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2018
卷号：7
期号：5
页码：4655-4661
DOI：10.15680/IJIRSET.2018.0705033
出版社：S&S Publications
摘要：The full subtractor design using hybrid logic and MTCMOS technique is proposed in this paper.
Subtractor is one of the arithmetic circuit and it plays a vital role in designing of VLSI circuit. The combinational logic
circuit is used in various field like DSP, low power VLSI design and also in microprocessor. Power dissipation is the
main issue in vlsi design. The objective of this project is to reduce the power dissipation. One of the method to reduce
the power dissipation is scaling. It causes the sub threshold leakage current which is the predominant component in the
total average power dissipation. In this paper we proposed a modified approach to decrease the power dissipation using
hybrid logic technique in full subtractor design. This design is used as basic cells for designing ripple borrow
subtractor. The simulation is performed at 1.8v using tanner tool in 180nm technology.
