首页    期刊浏览 2024年11月27日 星期三
登录注册

文章基本信息

  • 标题:VLSI Architecture for Reversible Multiplier-less Finite Impulse Response using Reversible Gate
  • 本地全文:下载
  • 作者:Yash Mishra ; Vaibhav Jindal
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2018
  • 卷号:7
  • 期号:6
  • 页码:6844-6850
  • DOI:10.15680/IJIRSET.2018.0706073
  • 出版社:S&S Publications
  • 摘要:In present improvement, the reversible logic configuration entrancing more consideration because of its low power utilization. Reversible logic is extremely huge in low-control circuit design. The basic reversible gate utilized for reversible logic amalgamation are Feynman Gate, Fredkin gate, Toffoli gate and peres gate and so forth. In this paper, a proficient engineering of FIR channel structure is displayed. For accomplishing low power, reversible logic method of operation is actualized in the plan. It additionally gives brief thought to manufacture snake circuits utilizing the essential reversible gate like peres gate and TSG gate.
  • 关键词:Finite Impulse Response; Distributive Arithmetic; Reversible Gate
国家哲学社会科学文献中心版权所有