期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2018
卷号：7
期号：6
页码：7513-7520
DOI：10.15680/IJIRSET.2018.0706125
出版社：S&S Publications
摘要：The main objective of this research paper is to design architecture for complex Vedic multiplier by
rectifying the problems in the existing method and to improve the speed by using the kogge stone adder with the help
of hybrid square technique. The Vedicmultiplier algorithm is normally used for higher bit length applications and
ordinarymultiplier is good for lower order bits. These two methods are combined to produce the high speed multiplier
for higher bit length applications. The problem of existing architecture is reduced by removing bits from the
remainders. The proposed algorithm is implementation Xilinx software with Vertex-7 device family.
