期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：6
页码：6239-6243
DOI：10.15680/IJIRCCE.2018.0606008
出版社：S&S Publications
摘要：PLL with redesigning of individual blocks like- PFD is designed using edge triggered D flip flop to
reduce area and static phase error, CP is designed using current mirrored structure to minimize the current mismatch
with increased output voltage and VCO has been designed using self bias differential ring oscillator to achieve low
jitter operation of PLL. The PLL is designed using 180 nm CMOS technology for high performance with 1.0 V power
supply.
