期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：6
页码：6257-6262
DOI：10.15680/IJIRCCE.2018.0606013
出版社：S&S Publications
摘要：we design a high speed 16x16 CMOS Vedic multiplier, for different configuration. All simulation is
done on tanner EDA TOOL 13.00 software. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm) for high
speed multiplication, and less number of transistor count. An adiabatic logic is used to design 16X16 CMOS Vedic
multiplier. Multiplication is one of the basic operations for any high speed digital logic system design, digital signal
processors or communication system. Primary issues in design of multiplier are area, delay, and power dissipation.
There are many algorithms like booth multiplier, array multiplier, vedic multiplier, compressor based Vedic multiplier
for overcoming this problems.
