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  • 标题:Design and Analysis of Novel Charge Pump Architecture for Phase Locked Loop
  • 本地全文:下载
  • 作者:Manoj Sharma ; Gajendra Sujediya
  • 期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
  • 印刷版ISSN:2320-9798
  • 电子版ISSN:2320-9801
  • 出版年度:2019
  • 卷号:7
  • 期号:1
  • 页码:64-71
  • DOI:10.15680/IJIRCCE.2019. 0701013
  • 出版社:S&S Publications
  • 摘要:Charge pump circuit is widely used in integrated circuits (ICs) due to the continuous power supply reduction which is dedicated to several kind of applications of low voltage phase locked loop (PLL), flash Memories & DRAM’s smart power, switched capacitor circuits, non-volatile memories, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, Radio frequency antenna switch controllers, etc. Charge pump are used in these application, basically it is DC to DC converter which have capacitor instead of an inductor or transformer for energy storage. Thereby it is able to generate to higher voltage than power supply voltage. Designing of charge pump depend on the structure of MOS transistors as switches. CMOS charge pump is appropriate for low voltage applications, can be activating with very low supply voltage. Conversely, the voltage drop and body effect of MOS transistor decrease the performance of the charge pump when the number of stages is lift up so that only 4-stage of various charge pump topologies have been implemented in this thesis such as Dickson, static, dynamic, with control scheme, with cross connected NMOS cell.
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