期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2019
卷号：7
期号：5
页码：3155-3160
DOI：10.15680/IJIRCCE.2019. 0705092
出版社：S&S Publications
摘要：This paper proposes a low-power and area-efficient shift register using pulsed latches.
The area and power consumption are reduced by replacing flip-flops with pulsed latches. This
method solves the timing problem between pulsed latches through the use of multiple non-overlap
delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift
register uses a small number of the pulsed clock signals by grouping the latches to several sub
shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed
latches was fabricated using a 0.18 $mu{rm m}$ CMOS process with ${rm V}_{rm DD}=1.8{rm
V}$. The core area is $6600 mu{rm m}^{2}$. The power consumption is 1.2 mW at a 100 MHz
clock frequency. The proposed shift register saves 37% area and 44% power compared to the
conventional shift register with flip-flops.
