期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2019
卷号：7
期号：5
页码：3161-3165
DOI：10.15680/IJIRCCE.2019. 0705093
出版社：S&S Publications
摘要：This work presents an elegant methodology using pulsed latch instead of flip-flop without altering the
existing design style. Pulsed-latch technique retain the advantages of both latches and flip-flops and thus one can
achieve both high speed and lower power consumption simultaneously. In this work, pulsed latch technique has been
used to reduce the delay of various shift registers without increasing any power consumption. In very high speed VLSI
circuits due to heavy pipelining there is requirement of low power edge triggered flip-flops. However, for low power
consumption in these very high speed VLSI circuits, the migration from flip-flop to pulsed latch technique has become
a great success. In the proposed work, non-overlapped delayed pulse clock has been used in pulse latch technique to
eliminate the timing problem between the pulsed latches. All the proposed shift registers have been designed in 180 nm
CMOS technology and their functionality have been verified using Cadence Virtuoso. From this work, it has been
concluded that, the pulse latch technique reduces the power consumption significantly in the designed registers and
overall there is an improvement in power delay product. Further, it is pertinent to mention that the proposed registers
require less number of transistors for their implementation as compared to conventional versions.
