期刊名称：International Journal of Advanced Computer Science and Applications(IJACSA)
印刷版ISSN：2158-107X
电子版ISSN：2156-5570
出版年度：2019
卷号：10
期号：12
页码：620-626
出版社：Science and Information Society (SAI)
摘要：Fault injection tools are designed to serve various
purposes, such as validate the design under test concerning reliability
requirements, find sensitive/critical locations that require
error mitigation, determine the expected circuit response in the
existence of faults. Fault Simulation/Emulation (S/E) applications
are involved in Field Programmable Gate Array (FPGA) based
design’s verification and simulation at the Hardware Description
Languages (HDL) code level. A tool is developed, named RASPFIT,
to perform code modification of FPGA designs, testing of
such designs, and finding the sensitive area of designs. This
tool works on the FPGA designs written in Verilog HDL at
various abstraction levels, gate, data-flow and behavioural levels.
This paper presents a technical aspect and the user-guide for
the proposed tool in detail, which includes generation of the
standalone application (an executable file of the tool for Windows
operating system) and installation method.
