摘要：While Artificial Neural Networks (ANNs) are implemented on FPGAs, first, a logic design is made for the desired ANN. Second, this design is coded in a hardware description language and is synthesized for a target FPGA chip. These procedures are time consuming, error prune processes and requires expert personal. In this study, an ANN data paths design tool (YTA) was developed to help automate the application of ANNs to FPGAs, to reduce the design and implementation time, and to minimize the expert requirements while mapping ANNs to FPGAs. YTA was tested with several test cases successfully. Using YTA, data paths can be designed and HDL codes can be produced automatically for given ANN in seconds.
其他摘要：Yapay Sinir Ağları (YSA) FPGA tabanlı sistemlerde gerçeklenirken; öncelikle istenen YSA için bir sayısal tasarım yapılır, ardından yapılan tasarım, bir donanım tanımlama dilinde kodlanarak hedef FPGA için sentezlenir. Bu işlemler zaman alan, uzman gerekti
