期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2020
卷号：98
期号：20
页码：3249-3259
出版社：Journal of Theoretical and Applied
摘要：This research aims to design a dump accumulator being capable of producing bit values in parallel from the sigma-delta ADC output signal that is serial in the reader of the Radio Frequency Identification (RFID) system. RFID system consists of two parts, namely a tag and a reader. The tag uses the delta-sigma ADC to convert the input signals from the sensor which, then, become the digital serial data that are transmitted to the reader. The reader uses the dump accumulator method to convert digital bits serially into 8-bit parallel resolution. The accumulator dump uses the counter and register latch circuits as output parallel bits. The results are divided into 3 time- periods, namely period 1 (T0) during the initialization and the synchronization, period 2 (T1) shows 8-bit binary data equivalent to 127(10), and period 3 (T2) shows 8-bit binary data equivalent to 128(10). By using 0.35 �m CMOS technology, the number of transistor hardware resources needed is 1022 transistors with a power dissipation of 28.5 mW. These results can save 77.42% using fewer transistors and are more efficient than the comb decimator method. This method contributes and enriches knowledge on the development of on-chip systems with serial to parallel signal processing for RFID devices.
关键词：ADC Delta-Sigma;Dump Accumulator;Efficiency;RFID;serial to parallel
