摘要：Graphene interconnects have been projected to out-perform Copper interconnects in the next generation Magnetic Quantum-dot Cellular Automata (MQCA) based nano-electronic applications. In this paper a simple two-step lithography process for patterning CVD monolayer graphene on SiO2/Si substrate has been used that resulted in the current density of one order higher magnitude as compared to the state-of-the-art graphene-based interconnects. Electrical performances of the fabricated graphene interconnects were evaluated, and the impact of temperature and size on the current density and reliability was investigated. The maximum current density of 1.18 ×108 A/cm2 was observed for 0.3 μm graphene interconnect on SiO2/Si substrate, which is about two orders and one order higher than that of conventionally used copper interconnects and CVD grown graphene respectively, thus demonstrating huge potential in outperforming copper wires for on-chip clocking. The drop in current at 473 K as compared to room temperature was found to be nearly 30%, indicating a positive temperature coefficient of resistivity (TCR). TCR for all cases were studied and it was found that with decrease in width, the sensitivity of temperature also reduces. The effect of resistivity on the breakdown current density was analysed on the experimental data using Matlab and found to follow the power-law equations. The breakdown current density was found to have a reciprocal relationship to graphene interconnect resistivity suggesting Joule heating as the likely mechanism of breakdown.
