摘要：Abstract This paper presents an area-efficient folded wavelet filter-based Electrocardiogram (ECG) detector for cardiac pacemakers. The modified folded undecimator based detector consists of Wavelet Filter Bank, QRS complex detector with Generalized Likelihood Ratio Test (GLRT) block and noise detector. A high-level transformation technique such as folding transformation and Cutset retiming are applied to the GLRT block in order to reduce the silicon area. Folding is a high-level transformation applied at the architectural level to enhance the performance of DSP architectures. It reduces the number of adders, multipliers and delay elements in the architecture. The Cutset retiming reduces clock period of the architecture by changing position of delay elements in the critical path. The folding transformation and cutset retiming implement the functional blocks of the GLRT circuit with minimum hardware. The modified folded ECG detector is tested for short term and long-term MIT-BIH databases. The results show that the modified folded undecimator detector has hardware savings and achieves sensitivity of 99.95%, positive prediction of 99.97% and Detection Error Rate (DER) of 0.061. The folded GLRT block architecture is synthesized with FPGA Zed board XC7Z010CLG484-1. Results show that the device utilization and power consumption are lesser than the conventional GLRT structure.
其他摘要：Abstract This paper presents an area-efficient folded wavelet filter-based Electrocardiogram (ECG) detector for cardiac pacemakers. The modified folded undecimator based detector consists of Wavelet Filter Bank, QRS complex detector with Generalized Likelihood Ratio Test (GLRT) block and noise detector. A high-level transformation technique such as folding transformation and Cutset retiming are applied to the GLRT block in order to reduce the silicon area. Folding is a high-level transformation applied at the architectural level to enhance the performance of DSP architectures. It reduces the number of adders, multipliers and delay elements in the architecture. The Cutset retiming reduces clock period of the architecture by changing position of delay elements in the critical path. The folding transformation and cutset retiming implement the functional blocks of the GLRT circuit with minimum hardware. The modified folded ECG detector is tested for short term and long-term MIT-BIH databases. The results show that the modified folded undecimator detector has hardware savings and achieves sensitivity of 99.95%, positive prediction of 99.97% and Detection Error Rate (DER) of 0.061. The folded GLRT block architecture is synthesized with FPGA Zed board XC7Z010CLG484-1. Results show that the device utilization and power consumption are lesser than the conventional GLRT structure.
