期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2020
卷号：10
期号：2
页码：1755-1763
DOI：10.11591/ijece.v10i2.pp1755-1763
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
关键词：area time product;CRC;critical path delay;LFSR;state-space transformation;
