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文章基本信息

  • 标题:Time-Predictable Computer Architecture
  • 本地全文:下载
  • 作者:Martin Schoeberl
  • 期刊名称:EURASIP Journal on Embedded Systems
  • 印刷版ISSN:1687-3955
  • 电子版ISSN:1687-3963
  • 出版年度:2009
  • 卷号:2009
  • DOI:10.1155/2009/758480
  • 出版社:Hindawi Publishing Corporation
  • 摘要:

    Today's general-purpose processors are optimized for maximum throughput. Real-time systems need a processor with both a reasonable and a known worst-case execution time (WCET). Features such as pipelines with instruction dependencies, caches, branch prediction, and out-of-order execution complicate WCET analysis and lead to very conservative estimates. In this paper, we evaluate the issues of current architectures with respect to WCET analysis. Then, we propose solutions for a time-predictable computer architecture. The proposed architecture is evaluated with implementation of some features in a Java processor. The resulting processor is a good target for WCET analysis and still performs well in the average case.

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