期刊名称：International Journal of Reconfigurable Computing
印刷版ISSN：1687-7195
电子版ISSN：1687-7209
出版年度：2010
卷号：2010
DOI：10.1155/2010/454506
出版社：Hindawi Publishing Corporation
摘要：Reconfigurable Computers (RCs) with hardware (FPGA) co-processors
can achieve significant performance improvement compared with
traditional microprocessor (𝜇𝑃)-based computers for many
scientific applications. The potential amount of speedup depends on the intrinsic parallelism of the target application
as well as the characteristics of the target platform. In this work,
we use image processing applications as a case study to demonstrate
how hardware designs are parameterized by the co-processor
architecture, particularly the data I/O, i.e., the local memory of the FPGA device and the interconnect
between the FPGA and the 𝜇𝑃. The local memory has to be used by applications that access data randomly. A typical case
belonging to this category is image registration. On the other hand,
an application such as edge detection can directly read data through the
interconnect in a sequential fashion. Two different algorithms of
image registration, the exhaustive search algorithm and the Discrete
Wavelet Transform (DWT)-based search algorithm, are implemented on
hardware, i.e., Xilinx Vertex-IIPro 50 on the Cray XD1 reconfigurable computer. The
performance improvements of hardware implementations are 10× and 2×, respectively. Regarding the category of applications that
directly access the interconnect, the hardware implementation of Canny edge detection can achieve 544× speedup.
