期刊名称：International Journal of Reconfigurable Computing
印刷版ISSN：1687-7195
电子版ISSN：1687-7209
出版年度：2009
卷号：2009
DOI：10.1155/2009/259837
出版社：Hindawi Publishing Corporation
摘要：This paper presents an improved interconnect network for
Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to
place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized
architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency
compared to VPR-style Mesh.
