期刊名称：International Journal of Reconfigurable Computing
印刷版ISSN：1687-7195
电子版ISSN：1687-7209
出版年度：2008
卷号：2008
DOI：10.1155/2008/751863
出版社：Hindawi Publishing Corporation
摘要：We investigate the
power and energy implications of using embedded
FPGA memory blocks to implement logic. Previous
studies have shown that this technique provides
extremely dense implementations of some types of
logic circuits, however, these previous studies
did not evaluate the impact on power. In this
paper, we measure the effects on power and
energy as a function of three architectural
parameters: the number of available memory
blocks, the size of the memory blocks, and the
flexibility of the memory blocks. We show that
although embedded memories provide area
efficient implementations of many circuits, this
technique results in additional power
consumption. We also show that blocks
containing smaller-memory arrays are more power
efficient than those containing large arrays,
but for most array sizes, the memory blocks
should be as flexible as possible. Finally, we
show that by combining physical arrays into
larger logical memories, and mapping logic in
such a way that some physical arrays can be
disabled on each access, can reduce the power
consumption penalty. The results were obtained from
place and routed circuits using standard
experimental physical design tools and a
detailed power model. Several results were also
verified through current measurements on a
0.13 𝜇m CMOS FPGA.
