Testing and process monitoring for a multifunction synthesizer - with reference to the HP 8904A Multifunction Synthesizer - includes related article on reliability of the HP 8904A - technical

Testing and Process Monitoring for a Multifunction Synthesizer

THE TEST STRATEGY FOR THE HP 8904A required a twofold solution. The first step was to understand the instrument and its performance characteristics. Because of its state-of-the-art design, there are no reliable, fast, and automated means of directly measuring some of its critical parameters. Also, its versatility makes it impossible to measure even a significant fraction of the waveforms it is capable of producing. Understanding the instrument at this level made it possible for us to find a concise set of parameters that can be measured accurately and quickly to verify that the unit under test is working correctly, and allowed us to make small design changes that enhanced testability.

The second step of the solution was to develop a test strategy for the HP 8904A that emphasized process control, rather than intense end-of-the-line testing. By testing critical parts and modules and then verifying the assembly process, the performance of the unit under test is assured quickly and inexpensively. Fault isolation and repair are also easier because problems are identified earlier in the production process.

The production test strategy for the HP 8904A takes advantage of the instrument's straightforward block diagram and the capabilities of the HP 3065 Automated Board Test System, on which all testing is done. The output board and the digital board determine the performance of the HP 8904A. The interface between these two is clearly defined and simple to characterize. The HP 3065 gave us built-in process control routines and freedom from making numerous connections during the test process. Fig. 1 shows a block diagram of the production flow for the HP 8904A.

Two primary functions in the HP 8904A need to be tested: the generation of correct digital data and the conversion of this digital data to an analog waveform. The first function is performed entirely on the digital board. The second is done entirely on the output board. After each of these is verified, what remains is to ensure that they are connected correctly.

DWSIC and Digital Board Test

Testing of the DWSIC is done in two phases. The primary testing is done at HP's Colorado Integrated Circuit Division where the IC is tested at the functional block level. The second phase of testing is an incoming inspection, which is a simple go/no-go test intended to catch catastrophic part failures. Incoming inspection also provides us with a basis for monitoring our process to ensure that we are not damaging parts in handling them. For this test the device under test is installed in an HP 8904A test bed and instructed to produce a variety of waveforms chosen to exercize as much of the chip as possible within a reasonable amount of test time. The resulting digital data is captured by a logic analyzer and compared with stored good data.

In the remainder of the digital board testing, logic and microprocessor components are used well within their performance limits. The board's performance is verified by conventional HP 3065 testing, the HP 8904A power-up self-check, and the ability of the board to pass the final check at the end of the line.

Output Board Test

Testing the analog output board begins with conventional HP 3065 in-circuit testing. Following in-circuit testing, a special test fixture equipped with coaxial probes is used on the HP 3065 to calibrate and verify the board under test. The tests are designed to verify the ability of the output board to convert any arbitrary stream of digital data into an analog waveform. Thus, one set of tests verifies the ability of the output board to reproduce all of the myriad waveforms that the DWSIC can generate. The output board test accomplishes this by measuring five primary characteristics: level accuracy, flatness as a function of frequency, amplitude linearity, noise and spurs, and delay distortion. From these five characteristics, the ability of the output board to reproduce a waveform can be predicted.

The biggest difficulty in making these measurements was to get the necessary accuracy. The test's measurement uncertainty had to be only a few hundredths of a percent out to 100 kHz for us to verify the amplitude flatness. At the same time, the test had to be fast enough and fully automated to meet our cost goals. This was achieved by making two-port transfer function measurements of amplitude and delay flatness with a network analyzer, using a high-speed reference DAC as a source driving the node between the HP 8904A's DAC and track-and-hold gate. The measurement is calibrated against a reference two-port network and a short length of 50-ohm coaxial cable, and gets its absolute reference from one-port voltage measurements. A separate two-port measurement is made to align the anti-aliasing filter. Two analyzers are used, the HP 3562A for frequencies below 100 kHz and the HP 3577A for those above 100 kHz. The test setup for the output board test is shown in Fig. 2.

Coaxial test probes and movable jumpers are designed into the output board for these measurements. The test station operator does not need to make any signal connections because the signals all come through the coaxial probes. The jumpers serve to isolate sections of the circuit and are moved according to prompts from the system. The reference DAC mentioned above and a switch matrix are built into the base of the output board test fixture.

Final Check

With the ability of the DWSIC to generate data confirmed by the chip tests, the ability of the digital board to issue the correct commands to the DWSIC verified by the HP 3065 test and the HP 8904A power-up self-check, and the data conversion performance of the output board verified by the special test fixture, what remains is to ensure that these pieces are assembled correctly. This is the job of final check. Performing a few fast, simple measurements on the outputs of the HP 8904A, this station provides us with a final process control check.

Statistical Quality Control and Process Monitoring

One major advantage of using the HP 3065 test system is the availability of the HP 1000 as the central processor for the entire production line. The standard HP 3065 test system automatically provides excellent process control data through the built-in data base and statistical quality control (SQC) package. The standard information is based on parametric test data, and provides such information as boards tested, boards failed, first-pass yields, test times, and cycle times.

The missing link to total quality control in the standard package is the ability to identify root causes through failure data. Our production line developed utilities on the HP 1000 to provide this missing information. An HP 3065-compatible failure-data-collection system was developed to collect failure data and symptoms from all printed circuit board and instrument assembly operations. This utility was appended to the standard HP 3065 test plan to allow the operator to call the failure screens and enter defect information and remarks when necessary. The utility also runs on a stand-alone terminal to be used at all nonautomated processes. Several of these terminals are distributed throughout the HP 8904A production line.

To eliminate redundant data collection, the data collected is reformatted and uploaded to the division's failure data base on a daily basis. This reformatting utility runs automatically each night and is virtually invisible to the production line. In addition to the reformatting process, the utility also creates, for every board and instrument assembly operation, a report containing information on workmanship and process defects. This provides a tight feedback loop for each process concerning the nature of the defect and where in the process the defect was discovered.

A third utility was developed to provide SQC reports on the failure data. This utility can be run at predetermined intervals. The reports provide more exhaustive information about each process step than the daily report (see Fig. 3). This program provides some of the information about the nonautomated stations that already exists for the computer-controlled stations through the HP 3065 SQC package. Additional information includes process performance measures, total repair times, a Pareto diagram of contributions from all processes, a Pareto diagram of where defects are reported, top failures by reference designators, top failures by part number, and a Pareto diagram of the types of defects being reported. In addition, a detail report can be prepared upon request.

Finally, analysis teams have been assembled to analyze the defects and the corresponding processes involved to determine the root causes for the recurring defects. This team then submits a proposal of possible solutions to management for consideration, approval, and implementation.

This entire process has provided unprecedented process control at Spokane Division. Much of the process was implemented without additional costs using routines already in place. Continuing support costs are minimized by a paperless reporting scheme that eliminates filling out forms or retyping reports.

Acknowledgments

We would like to thank Scott Smith, Mark Secrist, and Jerry McCandless for their efforts in helping to make this a successful project.

COPYRIGHT 1989 Hewlett Packard Company
COPYRIGHT 2004 Gale Group