Frequency and time interval analyzer measurement hardware - HP 5371 A Frequency and Time Interval Analyzer - technical
Paul S. StephensonFrequency and Time Interval Analyzer Measurement Hardware
FREQUENCY AGILE SYSTEMS pose many new measurement challenges. For example, how do you characterize modulation on a pseudorandom or unknown carrier? How do you capture relatively long time histories of frequency agile sources without using megabytes of memory? The design of the measurement hardware in the HP 5371A Frequency and Time Interval Analyzer had to deal with these challenges. This article will describe the design and operation of the measurement hardware, using a frequency-hopping radio measurement example.
Frequency Agile Measurements
The principal problem in frequency agile measurements is acquiring a time history of the source frequency. It is more efficient to count the number of signal periods during each sampling period while sampling at a rate tailored to the modulation bandwidth of the source under test than to record the entire waveform and postprocess it. The HP 5371A uses the former method to make frequency agile measurements, and thereby reduces the amount of data and processing required.
Other attempts to analyze frequency agile generators with standard instrumentation such as counters, spectrum analyzers, and modulation analyzers do not effectively handle frequency hopping signals in a dynamic environment. This stems from the constraints that standard instrument techniques impose on the measurement. These techniques require the hopping pattern to be repeated, slowed down, or known, thus limiting a user's understanding of the device's performance with respect to important parameters (e.g., switching transients, settling time, hopping distribution, and frequency or phase modulation riding on a hopping carrieer). For more information on characterizing frequency agile sources, see reference 1.
Fig. 1 shows schematic representation and typical functional characteristics of a hopping radio carrier used in spread-spectrum communications. The 1.6-ms blanked intervals between hops do not contain information and result in wasted memory when recorded with a waveform recorder or a digitizing oscilloscope.
To see the memory requirement differences between a waveform digitization method and the continuous count method of the HP 5371A, consider the three-hop waveform of Fig. 1. If F.sub.1., f.sub.2., and f.sub.3 are 48.5 MHz, 87.5 MHz, and 60 MHz, respectively, an eight-bit digitizer has to sample at twice the highest carrier frequency, or 175 MHz, for 27.2 ms to recover the modulated information. This results in 4.76 millions samples at one byte per sample. The HP 5371A only has to sample at twice the modulation bandwidth (2X20 kbits/s) to recover the desired frequency-versus-time information. At this 40-kHz rate the HP 5371A uses 960 samples at 10 bytes per sample for a total of 9600 bytes, versus 4.76 Mbytes for the waveform digitizer, or approximately 500 times less memory to obtain the desired frequency-versus-time data.
Before the introduction of the HP 5371A, dynamic testing of frequency hopping radios was usually limited to transmitters and receivers connected in a back-to-back configuration. Such a configuration uses a "golden receiver" to verify transmitter performance, and vice versa. A golden receiver is a unit that has been proven empirically to meet functional specifications.
This transmitter/receiver test approach has several limitations. Verifying and calibrating the performance of golden receivers is difficult. Often only a few units are available, making field repair difficult. Golden receivers can be poor analyzers for identifying problems within subsystem modules. Finally, information on performance margins cannot be gathered with this kind of go/no-go testing.
Measurement Hardware
The HP 5371A measurement hardware can be thought of as all the hardware used to acquire raw data from the binary outputs of the input amplifier. For example, when measuring a frequency-hopping radio, the RF output is preconditioned by the input board, which outputs a binary signal to the measurement hardware. The binary signal edges occur at the points where the transmitter input has crossed through the trigger level; these points are called events. The HP 5371A counts these events for some period of time, and by taking the ratio of events to time, computes the average frequency over this sampling period.
To avoid uncertainty in the number of events counted during the sampling time, a reciprocal counting technique is used to reduce measurement error. The reciprocal technique measures the time interval between the first and last events in the sample period while simultaneously counting the number of events. Therefore, unlike constant-sampling-rate systems, the sampling period is defined by synchronizing the sampling clock with the measured signal. The nth sampling period is the period between the first event after the nth sample-arm signal and the first event after tne (n+1)th sample-arm signal. This forces an integral number of events to occur during each sampling period, and thus makes the quantization error independent of input signal frequency. Second, it allows control, if desired, of the sampling period in real time by externally gating the instrument with a modulated sampling clock.
In this continuous count system, measurements are made in blocks, and within a block, the sampling periods are contiguous. Thus the last sample of the nth sampling period is the first sample of the (n+1)th sampling period.
In summary, the primary functions of the measurement hardware are counting events and measuring the time between the first and last events during a user-defined sampling period. This information is stored for processing after the completion of the data acquisition process.
System Block Diagram
Fig. 2 shows the HP 5371A system block diagram. As noted earlier, the input board preconditions the input signals and converts them to binary signal inputs for the measurement hardware. Other measurement hardware inputs include an external arming input (100 MHz) and an external frequency standard input (1, 2, 5, or MHz). In addition to these signal inputs, the measurement hardware receives measurement setup and control instructions from the microprocessor.
Signal outputs from the measurement hardware include gates 1 and 2, arm delays 1 and 2, and a 10-MHz frequency standard output. The gate and arm signals are binary signals indicating when measurement samples occur and when certain arming conditions are satisfied. These signals make it possible to use the flexible arming and gating to trigger additional instrumentation. The frequency standard output is a buffered output of the instrument's 10-MHz ovenized crystal frequency standard. When an external frequency standard is applied, this output matches the external standard's stability characteristics at 10 MHz.
In addition to these signal outputs, the measurement hardware provides
information to the microprocessor, including the state of the hardware and raw measurement data. Raw, unprocessed, binary data can also be rapidly acquired and transferred via the HP-IB (IEEE 488/IEC 625) to a host computer for subsequent processing.
Measurement Hardware Block Diagram
Fig. 3 shows the measurement hardware block diagram. The four major blocks are the sequencer, the event counters, the time base, and the memory system. The sequencer routes the input signals to the appropriate counting chain and generates the arming and latching signals for the event counters and the time base. The arming and latching signals depend on the input signal configuration, the sampling interval, and other arming qualifiers.
The two event counters count the events sent to them from the sequencer. They can be used for measuring and arming (e.g., event or time holdoff arming). The time base consists of two major subblocks: a counter chain that counts a synthesized, 500-MHz clock phase-locked to the internal or external frequency standard, and an interpolator which increases time resolution by a factor of ten over the 500-MHz time counter chain. The memory system consists of an 8K X 112-bit RAM operating at 10 MHz.
Measurement Example
We can see how each of these blocks functions during a measurement by using the example of a frequency-hopping radio. Suppose we have available from the radio under test both the RF output and the SYNC pulse defining the beginning of a pseudorandom hopping sequence. Assume that we want to examine, with one thousand samples, a 10-ms portion of the radio's hopping sequence, two seconds into the sequence. We must precisely delay the measurement for two seconds after the SYNC pulse. This can be accomplished by setting the HP 5371A to measure as follows: FREQUENCY Measurement Channel A Acquire 1 block of 1000 measurements TIME/INTERVAL Arming Mode Block Holdoff: After POSITIVE edge of EXT ARM Delay 2.000000000 s Then arm a block of measurements Sample Arm 10 [mu]s Acquisition Time/Block 10 ms
In general, this setup allows us to delay to any point after the external arming signal with 2-ns time resolution (8-second range) and then take up to 1000 continuous frequency measurements with sample periods as short as 600 ns. In this example, we are delaying two seconds and the sampling period is 10 [mu]s. The measurement is carried out by programming the sequencer to route the radio's RF output (connected to Channel A of the HP 5371A) to one of the event counters and the 500-MHz time base clock to the other event counter. The time basec clock to the second counter is gated on after receipt of the radio's SYNC signal by the sequencer. Finally, the 10-[mu]s sample-arm signal is selected as the qualifier for generating latching signals. The latching signals capture the event and time counts.
The event counters perform two functions: one counts the number of events on channel A (the radio's RF output), and the other counts a predetermined number of cycles of the 500-MHz time base clock (this generates the delay after the radio's SYNC signal). The event counter is preset to its terminal count minus the desired time delay divided by 2 ns. Then, after the sequencer enables the 500-MHz clock to this counter, the terminal count signal defines the selected delay arming.
In short, the measurement sequence is as follows. The SYNC signal in the external arming channel goes to the sequencer, enabling the 500-MHz time base to clock the event counter. The terminal count signal from this counter defines the block holdoff time, signaling the sequencer to start the 10-[mu]s sample-arm signal. Next, the sequencer synchronizes the sample-arm signal with the channel A events, creating latch signals for the RF input event counter and the time base. Finally, the latched values of the event counter and time base are stored in the memory system as raw data. After acquiring the data for all 1000 measurements, the processor assumes control and processes the raw data into measurement results. Fig. 4 shows the HP 5371A display of frequency versus time for this measurement.
This example outlines the basic hardware operation for the single-channel frequency measurement with time interval arming. For more information on other HP 5371A measurement configurations, see reference 3. The next section will cover the theory and operation of the four major subblocks of the measurement hardware in more detail.
Sequencer
The sequencer is one of two ASICs (application-specific integrated circuits) developed in-house for the HP 5371A. Fabricated using the HP5 process (a 5-GHz f.sub.T., bipolar process), this digital IC operates at frequencies in excess of 500 MHz. Containing over 2000 transistors and dissipating 3W, the sequencer occupies a 4.56 X 4.74-mm die packaged in a 72-pin printed circuit pin-grid array, or PCPGA (see Fig. 5). Mounting the die on the PCPGA's gold-plated, copper heat slug and attaching a three-finned machined aluminum heat sink allows the sequencer to operate with only a 10[deg.]C/W junction temperature rise above ambient at the air intake. This low thermal resistance keeps the junction temperature below 90[deg.]C under worst-case operation and contributes to the reliability of the sequencer.
As illustrated in the preceding measurement example, the sequencer serves as the signal-routing hub of the multiple-chip continous count system, and performs the signal switching, arming, and gating for the two input channels. 55 control bits in the sequencer configure it for the selected measurement and provide two-stage sequential arming for both stop and start arming. For two-channel time interval measurements, a parity detector keeps track of events on both channels to measure edge-pair relationships consistently. This feature eliminates bimodal distributions.
The sequencer architecture consists of two nearly identical channels, each containing an arming section and a clock section as shown in Fig. 6. The clock section selects the signal to be counted and routes it to the event counter. The arming section selects the sources of the latch signals for the event counters and the time base after the arming requirements for the measurement are satisfied. Designed to minimize crosstalk and jitter effects, the sequencer contributes less than 25 ps rms jitter to any measurement.
Event Counters
The HP 5371A has two 32-bit event counters. Each receives clocks and latches from the sequencer, and outputs latched count values on the fly, without resetting the counter. Each 32-bit counter consists of two 16-bit, cascadable, zero-dead-time (ZDT) counters. The ZDT counter chip is the other ASIC developed for the HP 5371A. Operating in excess of 500 MHz and, like the sequencer, fabricated in the HP5 process, the ZDT chip contains over 1500 transistors and dissipates 1.5W. It occupies a 4.56 X 3.43-mm die packaged in a 72-pin PCPGA. Fig. 7 shows the printed circuit board assembly containing the ASICs (six ZDT chips and one sequencer).
As shown in the measurement example, the ZDT chip counts events and outputs latched data to the measurement memory system. The ZDT chip also outputs the terminal count signal, which the sequencer can use as an arming qualifier. The ZDT chip accepts 16 bits of preset data and a 13-bit control word that sets the binary scaling ratio and the ZDT counter operating mode. Three address lines plus a chip-select signal control I/O on the multiplexed, bidirectional, 16-bit ZDT bus.
The ZDT latches count data on the fly at input frequencies in excess of 500 MHz. It achieves this with a cascadable architecture that synchronizes the latch command with the clock and then maintains this relationship through all 16 bits (see Fig. 8). Latching rates are limited by the clock-to-data-valid time of the counter (>10 MHz with two cascaded ZDT chips forming a 32-bit counter). Two fully parallel latch paths in the ZDT allow two latches to be taken back-to-back over the full operating bandwidth of the ZDT chip (>500 MHz). This overcomes some of the latch-rate limitations imposed by the clock-to-data-valid time of the counter. In addition, time interval measurements through zero time can be made using only one ZDT chain, because the parallel latch paths handle two totally independent latches.
Time Base
The purpose of the time base is to time-tag every latched event count, thereby building a time history of the latched event counts. From this, frequency or time interval can be analyzed as a function of time. As shown in Fig. 3, the time base consists of the time counter, which counts a synthesized 500-MHz clock phase-locked to the frequency standard, and the interpolator. Two ZDT chips form the 32-bit time counter, which operates like an event counter dedicated to counting the 500-MHz time base clock.
Latches to the time counter come from the sequencer much like latches to the event counter. They differ, however, from latches to the event counter because they must first be synchronized with the 500-MHz time base clock. This synchronization occurs before interpolation. Fig. 9 illustrates this measurement timing relationship.
The interpolator assembly performs two functions: it synchronizes the event latch signal with the 500-MHz time base clock, transforming it into a time latch, and it quantizes the time interval between the event latch and the time latch. Each time-tag consists of the time counter result, with 2-ns resolution, and the interpolator result, which quantizes the time difference between the time latch and the event latch with 200-ps resolution. These results are combined during measurement processing, giving 200-ps resolution for each time-tagged event count.
Interpolation Technique
The interpolation technique is based on a controlled race condition between the event and time latches. As shown in Fig. 10, the two latch signals go to a bank of nine high-speed D flip-flops which determine the relative phase between the two signals at nine equally spaced stages in the race. The race spans the 2-ns period of the time base clock.
With the race fixed such that the event latch signal is progressively delayed by 200 ps per stage (one time quantum per stage), the flip-flop outputs will quantize the original time interval between the two raced latches. Logical one and zero outputs indicate event latch leading and time latch leading, respectively. The stage in the race where the relative phase changes from event latch leading to time latch leading determines the original time interval between the latches within 200 ps, and thereby quantizes it. The flip-flops output a thermometer code, which is converted into a binary code and stored with the event count and time count in the memory system. The advantages of this interpolation technique over other time-to-digital converters are higher conversion rates and elimination of time-to-amplitude conversion circuits.
Memory System
The HP 5371A can measure signals as long as 8 s with resolution to 200 ps, and can count up to four billion events on both channels with 1-event resolution. These large dynamic ranges, 4 X 10.sup.10 and 4 X 10.sup.9., place heavy demands on the measurement memory width because the HP 5371A always stores full-precision raw data. Combining these raw data memory requirements with the measurement statusbit memory requirements results in a measurement memory width of 112 bits. The memory system also supports the 10-MHz maximum sampling rate, so the instrument has an information bandwidth potential in excess of 1 GHz.
The processed measurement memory depth depends on the mode of operation. The raw measurement memory depth is 8K samples. However, because of processing limitations, only 1000 individual processed measurements per block are available from the front panel (larger measurement sample sizes can be accumulated for statistical analysis by acquiring multiple blocks). Two-channel frequency, period, and totalize measurements require twice the raw data of the single-channel measurement, so only 500 measurements per block are available.
A host computer, reading raw binary data over the HP-IB, overcomes the processing limitations and can access the full 8K measurement memory depth. This nets 4095 individual processed measurements per block for single-channel measurements (some measurements require two pieces of raw data per processed measurement). For two-channel measurements the net is 2047 measurements per block.
Acknowledgments
Many people contributed to the design of the HP 5371A measurement hardware. William Lam designed the ZDT/sequencer board and was responsible for the ZDT ASIC development. Mark Wine and Victor Prince handled the DMA memory support and measurement control hardware. Jim Cole designed the time base synthesizer. Steve Carroll and Ron Jensen contributed to the interpolator hardware and the power supply design, respectively. The project team would also like to thank everyone at the Santa Clara Technology Center who contributed to the development and release of the sequencer and ZDT ASICs.
COPYRIGHT 1989 Hewlett Packard Company
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