A new high-performance 0.01-to-20-GHz synthesized signal generator microwave chain - design of the microwave chain in HP's 8370 and 70340 microwave signal generators - includes related article on internal pulse generator

William D. Baumgartner

Driven by a broadband YIG oscillator, the microwave chain only divides the oscillator output instead of multiplying and heterodyning like previous designs. The benefits include no subharmonics and higher-performance pulse and amplitude modulation. The major functions of the microwave chain are integrated on two microcircuits.

The microwave chain of the HP 8370 and HP 70340 synthesized signal generator families receives the output of the frequency synthesis section (2 to 20 GHz) and creates the leveled signal generator output signal (0.01 to 20 GHz).

The evolution of the microwave chain was driven by the needs of receiver test and local oscillator customers for higher performance, and the desire to reduce size, weight, and cost. The key performance goals were +8-dBm output power, [+ or -]dB level accuracy, no subharmonics, low harmonics (-55 dBc), fast (10 ns) high-fidelity pulses, and the capability for simultaneous pulse and deep (-60 dBc) amplitude modulation to simulate rotating-antenna transmitters (Fig. 1).

Previous architectures start with a 2-to-6.6-GHz fundamental band, multiply to 26.5 GHz, and postfilter with a YIG (yttrium iron garnet) filter. The frequency control, ALC, AM, FM, and pulse modulation are situated in the fundamental band for lower cost. The disadvantages associated with this approach are subharmonics, low power, slow pulse rise time (25 ns) because of the narrow YIG filter, and slow AM response when the AM is simultaneous with pulse modulation.

The HP 8370/70430 design takes advantage of new broadband gallium arsenide (GaAs) components to achieve the performance goals. Fig. 2 is a block diagram of the microwave chain. Subharmonics are eliminated by tuning a pair of broadband Y[G-tuned oscillators (YTOs) over a 2-to-20-GHz range. Six low-pass filters reduce harmonics to less than -55 dBc. The low-pass filters have wide bandwidths, so they do not slow or distort pulses. Deep AM is linear in dB per volt and flatness with frequency is corrected to achieve -60-dBc depth. AM and pulse modulation can be used simultaneously.

Broadband noise in the output of a synthesized signal generator affects the sensitivity of a receiver under test and degrades noise figure meter accuracy when the signal generator is used as a local oscillator In this design, AM noise is minimized by maintaining high power throughout the chain and not placing an amplifier at the output to boost power at the expense of noise. The YTO determines the AM noise at about 20 dB above the thermal noise level.

High Integration Level

To lower cost while increasing performance, the circuits after the YTO are integrated on two principal microcircuits, called the output module (Fig. 3) and the modulation module (Fig. 4). This maximizes performance by eliminating transitions, connectors, and cables that add loss and mismatch. The circuits are fabricated on PTFE*-based Duroid substrates and therefore can be relatively large without the circuit cracking encountered with both thick and thin films on hard substrates, which limits circuit sizes to about an inch or so. Both microcircuits are soldered into plated aluminum housings. To make it possible to use Duroid substrates with traditional chip and wire bonding, a bondable gold process was developed. Fabrication was simplified by careful tolerance analysis and the circuits are designed to eliminate RF adjustments, which can be costly. RF testing is done at the higher integration level. This improves yields over testing the lower-level circuits because a microcircuit can meet overall specifications and be accepted even though one of its components may exhibit high loss and another low.

Further integration is achieved by using the amplifiers for more than one function. The first amplifier in Fig. 2, in addition to boosting power and buffering the YTO from AM frequency pulling, acts as the ALC modulator. The second amplifier is part of the pulse modulator.

Binary Dividers

The use of binary frequency dividers to generate the 10-MHz-to-2-GHz band departs from the heterodyne systems used in previous broadband signal sources. The decision to replace the microwave mixers, oscillators, and amplifiers used in heterodyne down-converters with high-speed digital integrated circuits was driven by receiver test requirements for reduced noise, harmonics, and spurious signals. Advances in frequency dividers, broadband components for modulation and leveling, and high-density surface mount circuits for harmonic filtering make it possible to produce the divider system at a much lower cost than heterodyne systems of equivalent performance.

Heterodyning a section of the microwave band to the 10-MHz-to-2-GHz spectrum involves design compromises. Mixers used in the frequency translation inherently generate inband spurious signals. Drive levels to the mixer are reduced to minimize these spurs, decreasing the signal-to-noise ratio at the mixer output. Amplification used to bring the signal up to required levels raises the broadband noise floor as well. The mixing process duplicates the microwave phase noise characteristics in the RF band. Frequency division avoids these problems. Phase noise and spurious signals are reduced 6 dB with each octave of division. For a 70-MHz signal this results in a 36-dB improvement over heterodyne systems. The dividers handle moderate power levels and result in noise-floor improvement. s up to 20 dB.

Frequency division introduces some different design constraints. Output waveforms are square waves with a very rich harmonic spectrum. Third harmonics are only 9.5 dB below the fundamental and even-order harmonics, theoretically suppressed, require filtering. The harmonic specification of -55 dBc required filtering after the final amplification stages. Increased filtering to remove divider harmonics was added to the low pass-filter structures at minimal increase in product cost.

The modular nature of the cascaded dividers allowed low-cost frequency extension of the multifunction microcircuits from the 2-GHz low end of the YTO down to 1 GHz. Signal conditioning in the 1-to-2-GHz range is most economically done with the distributed components in the microcircuits. The extra octave allows the base source to supply the bands in the 1-to-2-GHz range, which used to require several generators or a complete heterodyne system. Surface mount technology provides repeatable RF performance for lumped-element design of the 10-MHz-to-1-GHz band.

Level accuracy is achieved by a ratioing ALC loop that is accurate over level and temperature and is corrected for power flatness variation over frequency.

Output Module

The first of the two multifunction microcircuits, the output module (Fig. 5), performs four functions. The first function is to couple a portion of the oscillator output back to the frequency sampler and the frequency control subsystem. Two directional couplers, each covering a YIG-oscillator frequency band, were designed for this purpose.

The second function of the output module is to provide switching to route the microwave signal from the appropriate YIG oscillator band through the microwave chain. Thirdly, the output module divides the YIG oscillator output in the 2-to-4-GHz range by two or four to generate signals from 0.5 to 1.0 GHz and 1.0 to 2.0 GHz. The 0.5-to-1.0-GHz band is used to drive the low-band circuit board, which generates outputs in the 0.01-to-1.0-GHz range.

The fourth function of the output module is microwave signal processing for the automatic level control (ALC) subsystem. A broadband directional coupler detector samples the average power incident on the synthesizer load and feeds back the sample to the level control loop circuitry. The variable-gain traveling-wave amplifier acts as the leveling loop control element, modulating the microwave power to the desired level.

A PTFE-based material, RT/Duroid 5880, was chosen as the substrate for the output module. This material has a low loss tangent (0.0009 at 10 GHz), can be processed in a printed circuit board shop (resulting in low cost), and can be used for large circuits that have complex outlines (unlike a large piece of alumina, which will crack when subjected to thermal stresses after being been laser-routed into a complicated shape).

Extensive use was made of CAD tools in the development of the components that are integrated into the output module. These tools included linear circuit simulators, system simulators, and graphical layout tools. One extremely useful program, written by Jeff Meyer of HP's Systems Solutions Division, computes the solution of Laplace's equation in a two-dimensional region. The program uses the method of moments to solve for the Laplacian potential. Properties of unconventional transmission line structures can be analyzed with the help of this program, and as a result, it was possible to design circuits not realizable with ordinary microstrip transmission line.

Switching in the output module is done with p-i-n beam-lead diodes. Two switches cover the 1-to-20-GHz frequency range. One is a double-pole, double-throw switch and the other is a single-pole, double-throw switch. It was a design goal to use as many primed components as possible to lower the assembly cost and ensure repeatable performance from unit to unit. The printed ground return shown in Fig. 6 provides a dc short while passing microwave signals from 2 to 20 GHz with a minimum of 20 dB return loss. The method of moments field solver program was used to design the 145-ohm characteristic impedance shunt stub in this circuit. Since the maximum impedance achievable with a microstrip transmission line on a 0.010-inch-thick RT/Duroid 5880 substrate is 110 ohms, it was necessary to modify the structure by etching the gap in the ground plane as shown in Fig. 7. The field solver was used to calculate the gap width required to achieve 145 ohms for a fixed top conductor width of 0.006 inch. By making H>>h, the transmission line impedance was made insensitive to manufacturing variations in the housing dimensions and in the circuit attach process.

The leveling coupler is an asymmetric, continuously tapered, parallel-line coupler. The nominal coupling is 20 dB from 2 to 20 GHz. An RT/Duroid 5880 overlay, clamped in place with a silicone sponge-rubber pad, is used to equalize the even-mode and odd-mode velocities. The method of moments field solver was used to design this structure by generating a table of odd-mode impedance values versus coupling gap. This table was used to synthesize a design using ideal coupled transmission lines. The directivity of the coupler is typically better than 16 dB to 20 GHz. Good directivity in the leveling coupler results in a good source match and output level accuracy for the signal generator. The over-lay and sponge clamp are thick enough so that currents are not induced in the package lid above the coupler. This allows a smooth transition to conventional microstrip. A broadband microstrip detector using planar doped barrier beam-lead diodes is therefore easily integrated with the coupler into a single housing. Integrating the leveling coupler detector with other circuits into one module yields substantial cost savings relative to previous signal generator block diagrams in which the coupler was a connectorized component purchased from an outside vendor and the detector was separately housed in an expensive package. The integrated design also allows the addition of a reference diode for temperature compensation. Figs. 8 and 9 show typical performance for the coupler detector.

Two additional microstrip couplers in the output module cover the 2-to-10-GHz and 10-to-20-GHz frequency bands. These couplers are used to feed back the signals from the frequency synthesis section to a frequency sampler. The construction of the 2-to-10-GHz coupler is similar to that of the leveling coupler. Its coupling ratio is 20 dB at 2 GHz and rolls off at 6 dB per octave to 10 GHz. The coupler was designed this way to reduce the level of harmonics incident on the frequency sampler. The 10-to-20-GHz coupler is entirely planar, making it very inexpensive to manufacture. It is a three-section, symmetric coupler with a nominal 33-dB coupling ratio. The even and odd modes are equalized by a printed capacitor at each end of the center section.

The broadband traveling-wave amplifier (described later) is housed in a hermetically sealed, ceramic package. This ensures reliable performance of this GaAs integrated circuit over varied environmental conditions such ns high humidity and temperature. Careful engineering ensures that the ceramic package does not degrade the microwave performance of the traveling-wave amplifier chip to 20 GHz.

Two static frequency dividers generate the 1-to-2-GHz band, which is switched back into the 1-to-20-GHz path, and the 0.5-to-1-GHz output drive for the 0.01-to-1-GHz divider band.

Modulation Module

The functions of the second microcircuit, the modulation module, include pulse modulation, amplitude modulation, and harmonic filtering, all from 1 to 20 GHz. This module also contains a low-distortion combining switch for the 0.01-to-1-GHz band. The modulation is implemented with a 0.010-inch thin-film alumina circuit on a 0.015-inch molybdenum carrier for thermal expansion matching and a hermetic thick-film alumina-packaged traveling-wave amplifier. The harmonic filtering and broadband combining switch are implemented on a 0.010-inch Duroid substrate. Fig. 10 is a diagram of the modulation module.

AM for the instrument. is provided by a modulator containing five shunt p-i-n diodes.(1) Originally designed for pulse modulation, in this case the modulator is used to provide 60 dB of logarithmic AM. The transfer function of the AM modulator is corrected as a function of modulation depth and frequency with gain and offset DAC (digital-to-analog converter) adjustments. Fig. 11 shows the deviation from linearity as a function of depth and frequency. The driving function departs from traditional AM in that it is logarithmic (- 10 dB/V). The log driving function is ideal for simulating large dynamic ranges like the deep nulls in an antenna scan pattern.

Pulse modulation for the instrument is implemented with three GaAs ICs: two attenuators and one traveling-wave amplifier. Specifications include 10%-to-90% pulse rise and fall times less than 10 ns, pulse on/off ratio > 80 dB, <10% pulse overshoot, [+ or -]dB pulse level accuracy (relative to the CW level), and <20-mV peak-to-peak video feedthrough. Fig. 12 shows a typical pulse and a typical pulse on/off ratio plot.

Aatenuators. The attenuators are series-shunt-series attenuators (Fig. 13). The series elements are common-gate FETs with 50-ohm resistors connected in parallel from drain to source. The shunt element is composed of four common-gate FETs connected in parallel with some transmission line spacing between them. This spacing contributes to a good match. It also results in a lower on/off ratio at low frequencies, where the spacing is negligible compared to a wave-length. The gates of the shunt FETs are driven by signals that are complementary to those that drive the gates of the series FETs. In the on state the series FETs are on and the shunt FETs are off, allowing the signal to pass. In the off state the series FETs are off and the shunt FETs are on, thus connecting the 50-ohm resistors that are in parallel with the series FETs to ground through the shunt FETs. This maintains a good match in the off state, unlike p-i-n diode modulators. This preservation of match in both states contributes to the good pulse envelope fidelity.

Amplifier. The traveling-wave amplifier is a seven-stage cascode design (Fig. 14). The gates of the common-gate FETs of the cascode are used to control the amplifier gain. In the on state, this control is high and the amplifier provides about 6 dB of gain. In the off state, this control is low, pinching off the FETs and turning the amplifier off. In this way the amplifier contributes to the pulse on/off ratio. The frequency response is dominated by the gate-to-source capacitance of the common-source FETs, so the on/off ratio is lower at higher frequencies. The traveling-wave amplifier thus complements the attenuators, compensating for loss and on/off ratio frequency response. Also, the match of the traveling-wave amplifier is maintained in both the on and off states.

Pulse Pedormance. Other factors that affect pulse on/off ratio are leakages and waveguide modes. The main leakage path is through the gate of the first series FET of the first attenuator, through the bias circuitry, and into the traveling-wave amplifier control. Bypassing is required to reduce this leakage to acceptable levels. Waveguide modes are suppressed with polyiron and narrow channels in the housing.

The pulse level accuracy is dominated by thermal effects in the traveling-wave amplifier. In the off condition, the amplifier cools down. When it is turned on, the gain is initially higher and drops as the traveling-wave amplifier heats up, with a time constant on the order of 10 [micro]s. Pulse level changes are typically about +0.5 dB from CW levels.

The pulse rise and fall times are dominated by the travelingwave amplifier switching time. The bypassing element requirements impose a lower limit on capacitance at the traveling-wave amplifier control input. Also, there are internal capacitors on each of the seven stages' second gates. The drive source impedance is nonhneaE the off-state impedance is low, and the on-state impedance is 50 ohms. A low impedance for the off state provides quick discharging of the bypass capacitance, and the matched impedance for the on state maintains good pulse envelope fidelity (a low-impedance driver in both states would cause pulse over-shoot and ringing). The driver used is simply a low-source-impedance circuit with a 50-ohm series output resistor and a Schottky diode in parallel with the 50 ohms (Fig. 10). For signal generator models without AM and pulse modulation the carrier circuit is replaced by a through line on a Duroid substrate.

Filters. The [less than or greater to]55-dBc harmonic performance of the instrument is achieved with a switched low-pass filter assembly. Six filters connected between two 1P6T (one-pole, 6-throw) p-i-n diode switches strip the harmonics from signals between 1 GHz and 20 GHz. The output combining switch also includes an extra throw for 0.01 to 1 GHz, making it a 1P7T switch. Harmonic filtering is not done for this path. The p-i-n diode used for this throw is a 1-[micro]s-lifetime diode, which maintains the harmonic performance down to 0.01 GHz. Fig. 15 shows typical second-harmonic performance; higher-harmonic performance is typically better.

The low-pass filters are distributed quasi-elliptic low-pass filters. They were computer optimized, emphasizing above-band spurious response. The lower three filters are asymmetric, which gives almost double the number of distinct transmission zeros in the stop band, and they are cascaded with five-element, higher-frequency, distributed low-pass filters to reduce spurious transmission bands.

The next two filters are optimized, symmetric, distributed Chebyshev low-pass filters. The last filter is only four shunt stubs on a 50-ohm line. This makes its loss lower, and it is easy to cut off the stubs to create a 50-ohm through line. The filter cutoff frequencies are 1.65 GHz, 2.75 GHz, 4.80 GHz, 8 GHz, 12.8 GHz, and 21 GHz.

Switches. The p-i-n switches are compensated to match the off diodes' capacitance. The input splitting switch has four series-series arms and two series-shunt-shunt arms, the latter for isolation and low loss at higher frequencies. The output combining switch has six series-shunt arms and a 0.01-to-1-GHz arm farther down the line. In the 0.01-to-1-GHz arm, the long-lifetime p-i-n diode's capacitance serves as the middle element of a five-element distributed low-pass filter.

The bias elements are distributed where possible for low cost, and all have capacitive feedthroughs to connect to a standard printed circuit board for bias switching circuitry.

An example will illustrate the operation of the switches (see Fig. 10). Consider the operation at 2 GHz. Only the LPF2 path is biased on and all other paths are biased off. This is accomplished by the application of +15V to J18 and a negative current for J4, J5, J12 through J14, and J24. J10 and J11 are each connected to 330 ohms to ground. The +15V on J18 forward biases CR4, CR21, and CR22, the current being set by the voltage and the 330-ohm resistors. CR10 is reverse biased by this same +15V, and the path through LPF2 is established. The other paths' negative currents forward bias CR2, CR9, CR11 through CR16, CR18, and CR19. This also sets up a reverse bias on CR1, CR3, CR5 through CR8, CR17, CR20, and CR23 through CR28. Thus the signal can only flow through LPF2. An important consideration is that the low-pass filters that are off do not disturb the match. For this reason series-only diode switches can't be used. For example, if CR9 were not present, LPFI's output reflection coefficient, which has magnitude unity and arbitrary phase because of the line lengths required to connect the circuit, could resonate with the capacitance of reverse biased CR3 to make a short circuit at the output switch's common pole. The input switch uses series-series diodes to combat the same effect, which works only because of the finite Q of the reverse biased diode's capacitance.

Low-Band Output Section

The low-band section (Fig. 16) provides the 10-MHz-to-1-GHz frequency band by dividing the 500-MHz-to-1024-GHz signal produced by the divide-by-four circuits in the output module microcircuit. The low-band input signal is divided, amplified, filtered to reduce harmonics, and detected for automatic level control (ALC). For modulated signal generator models, logarithmic AM and pulse modulators are inserted between the divider output and the amplifier input. The -55-dBc harmonic requirement inspired placement of filters at the end of the signal chain, easing the linearity constraint on the circuit blocks preceding the filters.

To minimize the impact on the cost of the 1-GHz-to-20-GHz base model, a modular design approach was taken. The low-band system consists of self-contained CW, modulation, and directional bridge detector printed circuit boards. Leveling is accomplished by ALC detection and drive signals with characteristics similar to the microwave system, allowing common use of the ALC circuits. This results in a system to which either a CW or a modulated frequency extension can be added without affecting the 1-GHz-to-20-GHz band.

Dividers. The divider block consists of a through path for the 500-MHz-to-1-GHz signal from the microwave output module microcircuit and six cascaded divide-by-2 stages to develop the full 10-MHz-to-1-GHz band. A broadband limiting amplifier is used to sum all seven octaves of divider outputs. The limiter's output is a 0-dBm square wave with good match. Power level at this point is relatively independent of divider drive levels. Because of the performance limitations of the dividers above 300 MHz and the finite bandwidth of the limiter, second harmonics are as high as -12 dBc. Third harmonics reach the -9.5 dBc level predicted by analysis of a square wave.

Output Amplifier. One output amplifier covers the entire 10-MHz-to-1-GHz band. It consists of four cascaded gain stages with a p-i-n diode modulator between the first two stages. The 25-dB-gain amplifier provides a minimum power of +24 dBm. A 40-dB-dynamic-range p-i-n diode modulator is used for ALC. For a stable ALC loop bandwidth over all power levels, a constant dB/volt transfer function is desired. A shaped exponential current driver ensures a 3-dB/volt drive characteristic that closely matches that of the microwave system.

Harmonic Filters. The low-band switched low-pass filter network covers two decades from 10 MHz to 1000 MHz. Implemented entirely as a lumped-element design with surface mount components for compact size, the network consists of 14 low-pass filters, three high-pass filters, the p-i-n diode switches, and drivers to select the switches. The low-pass filters are spaced two per octave, providing 45 dB of second-harmonic rejection at the low end of the band and greater than 55 dB of third-harmonic rejection. Stop-band spurious responses are lower than -50 dBc through 2 GHz to suppress the very rich harmonic spectrum of the dividers.

All filters are seventh-order elliptic designs. Elliptic filters have the very steep transition band required for second-harmonic rejection by virtue of transmission zeros in the stop band.

The network is separated into three frequency bands, each with an input high-pass filter to eliminate lower-frequency video components generated by the pulse modulator. Two filters covering 500 MHz to 1000 MHz are grouped together as one band to minimize insertion loss by keeping path lengths short. The six filters that span 64 MHz to 500 MHz serve double duty as harmonic filters for this range and as postfilters for the remaining six 10-MHz-to-64-MHz low-pass filters. The filters have stop-band spurious resonances primarily because of the self-resonance of the inductors used. For the lower-frequency bank of filters these occur below the 1000-MHz system bandwidth. High-order divider harmonics would degrade the -55-dBc harmonic performance should they fail on a stop-band spurious response. All signals in the 10-MHz-to-64-MHz filter bank are subsequently routed through a filter in the 64-MHz-to-500-MHz bank to suppress the spurious responses. For example, when the 32-MHz filter is selected, the signal is further filtered by the 256-MHz low-pass filter. Spurious resonances of the remainder of the filters are above 1000 MHz, where the gain roll-off of the output amplifier effectively reduces the high-frequency harmonic content of the dividers.

Long-lifetime surface mount p-i-n diodes are used in all low-frequency filter paths to prevent distortion at higher power levels. The insertion loss of the network is typically 3.5 dB. The network occupies a 3.5-by-4.5-inch area.

Amplitude Modulation. The low-band logarithmic amplitude modulator is a broadband 10-MHz-to-1000-MHz design. It is used with an open ALC loop, in the hold position of the track-and-hold mode. This avoids reduction of modulation bandwidth during simultaneous pulse modulation and AM, a limitation of previous ALC systems. Also, AM depth is not restricted to the floor of the level detector. Since there are separate modulators for AM and ALC, the full 60-dB AM range is available at all power levels. However, without ALC feedback to correct for inaccuracies or drift, the modulator must exhibit constant drive sensitivity and flat frequency response at all attenuation levels.

The modulator is a three-stage differential amplifier capable of 75-dB dynamic range at 1000 MHz (Fig. 17). Each stage consists of two cross-coupled differential pairs. Cross coupling results in a transfer characteristic that is the gain difference of each pair. Gain is controlled by varying the difference current in the emitters of the differential pairs. Minimum gain occurs when both pairs are driven at exactly the same current level, the signal at one collector canceling the signal from the other.

The first stage (Fig. 18) is always in the limiting mode, driven at a high RF level. The output signal is independent of the 10-MHz-to-1000-MHz level and is equal to [I.sub.mod][R.sub., the difference current of the two pairs times the collector resistance. At low attenuation levels this signal is enough to fully switch stages 2 and 3. The Final output is again the difference current, [I.sub.mod], into the load resistance [R.sub.c]. As attenuation is increased, [I.sub.mod] is reduced. Eventually the signal from the first stage is too small to fully switch stage 2 and stage 2 cannot fully drive stage 3. The gain of these output stages is now dependent on the drive levels of the previous stage as well as the difference current, [I.sub.mod], at the differential emitters.

When the output signal is plotted as a function of [I.sub.mod] on a logarithmic scale, gain is seen to vary from 20 dB per decade change of [I.sub.mod] at low attenuation levels to 60 dB per decade change of [I.sub.mod] at high attenuation levels. Generating [I.sub.mod] from an exponential current source and then shaping the input to the exponentiator results in a-10-dB/volt modulation input characteristic (Fig. 19).

A minimum current, Ibias, is always run through both sides of the differential pairs to keep the transistors operating at a high gain-bandwidth point. This prevents the modulator frequency response from changing when the modulator drive is changed. Temperature stability is inherent because the stage gain is the difference between the two monolithic differential pairs, which tend to drift at the same rate.

Pulse Modulation. The 10-to-1000-MHz pulse modulator is composed of two single-pole, double-throw GaAs switches. On-off ratios greater than 90 dB are achieved with just two devices. An interesting feature of this modulator is the three-speed variable-rise-time control. This feature is necessary because the switched low-pass filter network follows all of the modulation. If the RF rise time is too fast going into a filter, the output of the filter shows an excessive amount of ringing and overshoot. The variable RF rise time is achieved by low-pass filtering the complementary control voltage inputs of the GaAs switches. Passive RC filters are used, with an analog switching network to select one of three sets of filters. The three rise times correspond to three frequency bands: 10 to 64 MHz, 64 to 500 MHz, and 500 to 1000 MHz.

Power Leveling

The automatic level control (ALC) system is a feedback loop that allows precise control of the microwave output power level over the signal generator's full output power range (from maximum power to -90 dBm) and frequency range (0.01 to 20 GHz). The main components of the ALC system are shown in Fig. 20. The microwave output power is sampled by the microwave coupler and detected by the diode sensing element. The diode transfer function is highly nonlinear and varies significantly with temperature. However, over a large part of its dynamic (operating) range, the detector's dc voltage output changes by approximately a decade for a 10-dB change in microwave input power. If this detector output voltage is logarithmically converted, the overall transfer function of the detector and the logarithmic amplifier is approximately a constant. At 25 degrees C this constant varies from 4 to 6 mV per dB of input power change.

Traditionally, logarithmic amplifiers have been used at the outputs of microwave detectors to compensate for the non-linear diode transfer function. The transfer function of the microwave amplifier gain as a function of gain control voltage complements that of the detector and log amplifier and is instrumental in the determination of the system loop transfer function and the control system bandwidth. The gain of the microwave amplifier can be adjusted over approximately a 35-dB range by applying a control voltage to the second-gate control line. This increases the harmonic distortion generated by the amplifier, especially near the device pinch-off voltage, but the harmonics are adequately filtered before entering the microwave coupler and therefore have minimal effect on the level accuracy.

As shown in Fig. 21, the transfer function of the traveling-wave amplifier output power as a function of control voltage is approximately linear in dB/volt over most of the output adjustment range. The rest of the components in the feed-back loop are linear in volts/volt (integrator, microwave filters, cables, etc.). Therefore, if the cascade of linear components has gain A, the loop gain will be approximately A(5 mV/dB)( 10 dB/V).

Once the loop gain is set, the control loop bandwidth can be set by choosing the RC values of the integrator. Changes in loop gain will directly affect loop bandwidth. Since the detector transfer function changes as the diode is operated at higher power levels and the traveling-wave amplifier gain control saturates at higher control line voltages, there is a decrease in loop gain at high vernier levels. This in turn causes a corresponding decrease in loop bandwidth. The loop bandwidth is least at high frequencies and high power levels. The loop bandwidth is greatest at lower frequencies and low vernier levels. The integrator pole was chosen so that amplitude level switching time is short enough at the minimum loop bandwidth, loop peaking is minimized, and loop stability is ensured at the maximum loop bandwidth.

The integrator provides the dominant pole in the system and the next closest pole is from the log amplifier. As the detector voltage decreases, the log amplifier gain increases and its pole decreases in frequency. A limiter on the log amplifier gain at low input levels establishes the minimum pole frequency. This prevents loop instabilities during transients in which no microwave signal is present at the detector input. The next pole is set at 100 kHz on the traveling-wave amplifier second gate control line. This reduces noise outside the ALC loop bandwidth.

The dynamic characteristics of the loop have been reviewed and the need for the log amplifier in the feedback path has been discussed. The log amplifier output voltage [V.sub.o] is:

[V.sub.o] = [V.sub.t]ln([V.sub.diode]/[I.sub.sat]R).

There are two temperature dependent terms: [V.sub.t], which varies linearly with temperature, and a less predictable parameter, [I.sub.sat] . [I.sub.sat] and [V.sub.t] are parameters of the logging transistor. Statically, incorporation of the log amplifier in the feedback path presents a problem and the nonlinear and thermal characteristics of the diode need to be compensated. Historically, these problems have been overcome through extensive characterization of diodes and log amplifier shaping techniques. Once data has been acquired on a diode's characteristics, temperature compensation is applied to the reference path of the integrator. This method is inherently less accurate because of the assumption that all diodes have identical characteristics. The dual log leveling loop circumvents both the thermal and the nonlinearity problems. The effect of the dual logging transistor is that the error terms associated with [V.sub.t] and [I.sub.sat] are ratioed out. The reference detector in thermal contact with the feedback diode has a similar effect: the nonlinearities and thermal variations of the diodes are also ratioed out.

The input to the reference detector is a 1-MHz sinusoidal signal. Its level can be precisely controlled with a DAC and it exhibits excellent temperature stability. Thus, given the symmetry of the reference path to the feedback path, the coupled microwave output power will be adjusted by the action of the servo loop to be identically equal to the power of the reference. All dynamic errors of the loop are calibrated out with the vernier calibration algorithm. In this algorithm, the DAC is stepped and the instrument output power is recorded. Then a curve is fit to the pairs of points, giving power out as a function of DAC number. Thus, for any desired output power, the required DAC value can be computed. This eliminates the need for adjusting operational amplifier offset voltages and compensates for slight differences in detector characteristics.

The most significant remaining sources of error within the feedback system are differential thermal characteristics in the detector and logging transistor pairs. The temperature drift caused by these effects is less than [+ or -] 0.15 dB over the operating range of 0 degrees C to 55 degrees C. The largest sources of error are changes in conductor losses of components outside the feedback loop, such as the cables and the step attenuator. This accounts for an additional [+ or -] 0.25 dB of the level accuracy error budget.

A frequency flatness calibration digital correction table is generated to compensate for component losses outside the leveling loop and correct the frequency unflatness of the microwave coupler, thereby relaxing the design constraints on the coupler. HP's proprietary planar doped barrier diodes are instrumental in achieving the tight level accuracy specifications over the vernier operating range (see Fig. 22). Unlike their Schottky diode counterparts, planar doped barrier diodes have consistent frequency flatness independent of operating power level.

Acknowledgments

In any successful project there are many people who contribute to the overall success. Thanks to Soojin Choi for developing the bondable gold-on-Duroid-substrate process and ensuring the design was manufacturable during the design process, to Eddie Plantillas for development of the test system, to John Duran for endless hours of testing of the environmental and prototype units, to Harrell Huckeba for partial development of the modulation module, to Yvonne Vieira for her skill in building the breadboards and prototypes, to Ed Cirimelle for flawless housing designs, to Marlene Hartigan for keeping us organized in tracking our defects and solutions, to Jim Logie for setting up the lab parts and helping us out of the polyiron cracking problems, to the team at the Microwave Technology Division--Morgan Culver, Gene Burdick, Ted Shimkowski, and Sig Johnsen--for development of the ceramic hermetic traveling-wave amplifier package, to Orrin Baisden and AI Bates for keeping the material straight, and to Mark Johnston for coding all the algorithms and juggling an incredible amount of inputs.

Reference

1. M.K. Koenig, "A High-Speed Microwave Pulse Modulator," Hewlett-Packard Journal, Vol. 42, no. 2, April 1991, pp. 34-36.

Internal Pulse Generator

This section describes the internal pulse modulation source in the HP 83732A microwave signal generator. The pulse generator is digitally based, and is implemented in a programmable gate array. Pulse width, pulse repetition interval, and pulse delay can be independently controlled.

The pulse generator can operate in five different modes: external pulse mode, internal pulse mode, triggered pulse mode, pulse doublet mode, and gated pulse mode.

External Pulse Mode

In external pulse mode the pulse generator simply passes a TTL-level input signal from the pulse/trigger input to drive the pulse modulator. The input polarity can be inverted. The input signal is buffered and passed on to the video output.

Internal Pulse Mode

In internal pulse mode the pulse generator provides TTL-level signals to drive the pulse modulator of the HP 83732A and the sync and video outputs on the front panel. Three parameters can be controlled from the keyboard or through HP-1B (IEEE 488, IEC 625)commands. These are the pulse repetition interval, the pulse width, and the delay from sync to video. The sync output pulse width is a fixed 50 ns, while the video output pulse width is programmable. The RF output pulse width is the same as the video output minus RF pulse compression. Both the sync and video outputs have a nominal 50-ohm output impedance. They provide +5 volts into high impedance and greater than +2.5 volts into a 50-ohm load. In this mode, "negative delay" is possible(see below).

Triggered Pulse Mode

In triggered pulse mode the pulse generator provides the same TTL-level signals as in internal pulse mode. However, the pulse/trigger connector on the front panel is used as a trigger input. This externally supplied trigger signal provides the pulse repetition interval. It is rising-edge triggered from a pulse greater than 25 ns wide. Only the pulse width and delay parameters are variable. The sync output is generated at a fixed minimum time delay from the pulse/trigger input. The pulse generator rejects triggers during the middle of a cycle. Thus, the pulse generator can divide an external trigger source in this mode.

Pulse Doublet mode

In pulse doublet mode the pulse generator operates in the same manner as in triggered pulse mode, but with additional capability. The external trigger signal is also passed through to the pulse modulator as in external pulse mode. Thus, it is possible to get two pulses out for each input pulse. The first is just the external pulse mode output, while the second is controlled by the delay and pulse width settings for triggered pulse mode. If the two pulses overlap, then just one large pulse results, with the leading edge determined by the external input signal and the trailing edge determined by the pulse generator.

Gated Pulse Mode

In gated pulse mode the pulse generator responds to the external input in a level-sensitive manner, While the external input is high, the pulse generator free-runs as in internal pulse mode. If the external input is low, no pulses are generated. The pulse generator triggers on the rising edge of the external input, and always outputs complete pulses. Only the pulse width and the pulse repetition interval are variable.

Implementation

The pulse generator is based on a single-counter design. Timing of width, rate, and delay are all determined from one 24-bit up-counter. Fig. 1 shows the basic architecture. The counter counts up from zero to (N-1), giving a total count length of N. When the count value matches the control word, a pulse is generated that synchronously resets the counter to zero and the cycle starts over. The reset pulse is also the sync output pulse, marking time zero of the cycle.

There are two other registered comparators. One marks the beginning of the video pulse and the other marks the end. The control words are 24-bit video begin and video end inputs. A small set-reset state machine converts these pulses into the actual video output pulse. Fig. 2 shows the details. Video begin and video end signals occurring simultaneously are defined as a reset signal, making a zero pulse width possible. Also, negative delay from the sync output to the video output is possible because of the arbitrary placement of the video begin and video end pulses.

The entire pulse generator is contained in one Xilinx XC3030 field-programmable gate array. An 88-bit serial interface is included in the gate array to allow loading all of the necessary pulse generator control data from the main instrument microprocessor. The pulse generator is clocked at 40 MHz, so all programmable parameters have 25-ns resolution.

This design is approximately equivalent to 25 to 30 SSI/MSI standard parts.

Douglas A. Larson

Development Engineer

Stanford Park Division

COPYRIGHT 1993 Hewlett Packard Company
COPYRIGHT 2004 Gale Group