期刊名称：International Journal of Computer, Information, and Systems Science, and Engineering
印刷版ISSN：1307-2331
出版年度：2007
卷号：1
期号：2
出版社：World Academy of Science, Engineering and Technology
摘要：An effective approach for realizing the binary tree
structure, representing a combinational logic functionality with
enhanced throughput, is discussed in this paper. The optimization in
maximum operating frequency was achieved through delay
minimization, which in turn was possible by means of reducing the
depth of the binary network. The proposed synthesis methodology
has been validated by experimentation with FPGA as the target
technology. Though our proposal is technology independent, yet the
heuristic enables better optimization in throughput even after
technology mapping for such Boolean functionality; whose reduced
CNF form is associated with a lesser literal cost than its reduced
DNF form at the Boolean equation level. For cases otherwise, our
method converges to similar results as that of [12]. The practical
results obtained for a variety of case studies demonstrate an
improvement in the maximum throughput rate for Spartan IIE
(XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic
families by 10.49% and 13.68% respectively. With respect to the
LUTs and IOBUFs required for physical implementation of the
requisite non-regenerative logic functionality, the proposed method
enabled savings to the tune of 44.35% and 44.67% respectively, over
the existing efficient method available in literature [12].
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