期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2006
卷号：6
期号：9A
页码：216-222
出版社：International Journal of Computer Science and Network Security
摘要：Integrating the reconfigurable logic and the host processor can eliminate the communication bottleneck that is present in current custom computing units. This integration is of great advantage if the reconfigurable block consumes less power. Once power optimization of the VRC is possible, the combined system can provide high speed computing with low power consumption. This paper describes experiments conducted to analyze the power consumed by the individual processing elements of a virtual reconfigurable circuit (VRC) according to the functionality performed. The experiment is performed on a model VRC designed to perform sensor validation and automatic functional reconfiguration in case of occurrence of single or multiple sensor faults. The power analysis done in this work will assist to estimate how the use of VRC’s influence the integration of FPGA based evolvable systems with host processor and can facilitate reconfigurable computing to enter the mainstream and provide high performance benefits
关键词：Virtual Reconfigurable circuit, Power Analysis, Evolvable hardware
