出版社：International Digital Organization for Scientific Information Publications
摘要：In this paper we present a new design of current mode full adder cell, which uses two threshold
detectors based on majority function. The proposed new full adder demonstrates better performance
compared to the conventional current mode full adder, especially in delay, accuracy and area. Both of the
new and the conventional full adders are simulated at 0.18 μm CMOS technology with 1.8v Vdd, using
Hspice. We considered that the unit of current is equal to 20μA. To have a realistic simulation environment,
we cascaded five full adder cells and focused on one of the middle cells. The simulation results show that
the delay of the new current mode full adder cell has about 51% reduction, compared to the best existing
counterpart.
关键词：VLSI · cmos circuit · full adder · current mode · voltage mode · multiple valued logic
