期刊名称：International Journal of Computer Systems Science and Engineering
印刷版ISSN：1307-430X
出版年度：2008
卷号：04
期号：03
页码：234-234
出版社：World Academy of Science, Engineering and Technology
摘要：For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16¡Á16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
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