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  • 标题:High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells
  • 作者:Reza Faghih Mirzaee ; Mohammad Hossein Moaiyeri ; Keivan Navi
  • 期刊名称:International Journal of Computer Systems Science and Engineering
  • 印刷版ISSN:1307-430X
  • 出版年度:2008
  • 卷号:04
  • 期号:04
  • 页码:304-304
  • 出版社:World Academy of Science, Engineering and Technology
  • 摘要:In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18μm CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.
  • 关键词:Bridge Style, Dynamic Logic, Full Adder, High Speed, Multi Output, NP-CMOS, Zipper.
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