The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper proposes a solution for reducing the number of Wrapper Boundary Register (WBR) cells. By utilizing the WBRs of the surrounding cores to transfer test stimuli and responses, the WBRs of some cores can be removed without affecting the testability of the SoC. We denote the cores without WBRs as light-wrapped cores and present a new modular SoC test architecture for concurrently testing both the wrapped and the light-wrapped logic cores. Since the WBRs of cores that transfer test stimuli and test responses for light-wrapped cores become shared resources during test, con?icts arise during test scheduling that will negatively impact the test application time. The algorithm for SoC test scheduling and light-wrapped logic cores works under multiple constraints (test power dissipation, test resources and test priorities) and applies a Power Swarm optimization based optimum search for a solution to the scheduling problem. We consider the experiments on several SoC benchmark circuits and demonstrate that, with an acceptable increase in test application time, the number of WBRs can be signi?cantly decreased.