期刊名称：BVICAM's International Journal of Information Technology
印刷版ISSN：0973-5658
出版年度：2012
卷号：4
期号：1
出版社：Bharati Vidyapeeth's Institute of Computer Applications and Management
摘要：Network on chip is a scalable and flexible communication architecture for the design of core based System-on-Chip. Communication performance of a NOC heavily depends on routing algorithm. XY routing algorithm is distributed deterministic routing algorithm. Odd-Even (OE) routing algorithm is distributed adaptive routing algorithm with deadlock-free ability. DyAD combines the advantages of both deterministic and adaptive routing schemes. Key metrics which determines best performance for routing algorithms for Network-on-Chip architectures are Minimum Latency, Minimum Power and Maximum Throughput. We demonstrated the impact of traffic load (bandwidth) variations on average latency and total network power for three routing algorithms XY, OE and DyAD on a 3x3 2-dimensional mesh topology. The simulation is performed on nirgam NoC simulator version 2.1 for constant bit rate traffic condition. The simulation results reveals the dominance of DyAD over XY and OE algorithms depicting the minimum values of overall average latency per channel (in clock cycles per flit) as 1.58871, overall average latency per channel (in clock cycles per packet) as 9.53226, overall average latency (in clock cycles per flit) as 26.105, and total network power as 0.1771 milliwatts, achieved for DyAD routing algorithm.
