期刊名称：International Journal of Reconfigurable Computing
印刷版ISSN：1687-7195
电子版ISSN：1687-7209
出版年度：2012
卷号：2012
DOI：10.1155/2012/716984
出版社：Hindawi Publishing Corporation
摘要：Parameterised reconfiguration is a method for dynamic circuit specialization on FPGAs. The main advantage of
this new concept is the high resource efficiency. Additionally, there is an automated tool flow, TMAP, that converts a hardware
design into a more resource-efficient run-time reconfigurable design without a large design effort. We will start by explaining
the core principles behind the dynamic circuit specialization technique. Next, we show the possible gains in encryption applications
using an AES encoder. Our AES design shows a 20.6% area gain compared to an unoptimized hardware implementation and a
5.3% gain compared to a manually optimized third-party hardware implementation. We also used TMAP on a Triple-DES and an
RC6 implementation, where we achieve a 27.8% and a 72.7% LUT-area gain. In addition, we discuss a run-time reconfigurable
DNA aligner. We focus on the optimizations to the dynamic specialization overhead. Our final design is up to 2.80-times more
efficient on cheaper FPGAs than the original DNA aligner when at least one DNA sequence is longer than 758 characters. Most
sequences in DNA alignment are of the order 213.
