摘要：SRAM-Filed Programmable Gate Arrays (FPGA) have become one of the most important carriers of digital electronic system because of its many inborn advantages. However, as manufacture of Integrated Circuit evolves towards Very Deep Sub-Micron technology, FPGA designers must be careful of circuit’s Single Event Upset (SEU) susceptibility when used in hostile environment, such as avionics and space applications where reliability is vital. We proposed a SEU-fault emulation platform to evaluate circuit’s SEU mitigation performance. The platform does not need any external circuit or micro controller to manage fault emulation process compared with existing approach. Source codes of Circuit Under Test (CUT) do not need to be modified or intruded with any component. It is a non-intrusive testing. Communication between host-computer and emulation board is minimized to accelerate fault injection speed. Experimental result shows that a single fault injecting (including Multi-Bits-Upset) only costs 29us. A circuit state reloading technology is exploited to increase emulation efficiency. Moreover, in the field of evolvable hardware, genetic operations can be reconfigured and its fitness can be evaluated on-line using the proposed fast dynamic reconfiguration method, which is useful for implementing self-repair and self-evolutionary hardware.
