Nowadays, telecommunication networks are passing through a rapid evolution. The introduction of novel services in high-speed networks such as Asynchronous Transfer Mode (ATM) requires different handling of connections. While real-time applications usually require low end-to-end delay and delay jitters, and are not very sensitive to loss within an acceptable range, there exist applications that require very low loss rates but are not concerned of delay or delay jitters. The concept of designing Multistage Interconnection Network (MIN) capable of operating with and without cell loss and cell delay sensitiveness can be a reasonable alternative. This paper is divided into two subjects. In the first a new switch architecture is depicted. Our proposed switching architecture and protocol handles connections' different Quality of Service (QoS) requirements with different mechanisms. We introduce four cell types that can be mapped to the existing ATM services. The investigation of such a complicated system as an ATM switch, requires lot of simulation time in any conservative simulation environment. To achieve shorter simulation time, our simulation platform was designed for Parallel Discrete Event Simulation (PDES) environment. The extended features and mechanisms of our MIN involves individual solutions during interaction among processes, which are addressed in the second part of the article.