期刊名称：International Journal of Research and Innovation in Computer Engineering
电子版ISSN：2249-6580
出版年度：2011
卷号：1
期号：2
页码：53-56
出版社：Innovation Science Publications
摘要：This paper describes an efficient hardware realization of the Advanced Encryption Standard (AES) algorithm using FPGA. The AES also known as the Rijndael algorithm was selected as a Standard on October 2, 2000 by National Institute of Standards and Technology (NIST). Encryption algorithms are used to ensure security of transmission channels.We use AES 128- bit block size and 128-bit cipher key for the implementation on Xilinx Virtex 5 FPGA. Xilinx ISETM 12.4 design tool is used for synthesis of the design. The design is coded using Very High Speed Integrated Circuit Hardware Description Language(VHDL). In our fully pipelined design, the operational frequency can be upto 347.6MHz and the throughput can be upto 44.5Gbits/s. The proposed fully pipelined AES realization achieves high throughput requirements and can be used for cryptology applications such as data security.
