期刊名称：International Journal of Signal Processing, Image Processing and Pattern Recognition
印刷版ISSN：2005-4254
出版年度：2012
卷号：5
期号：3
出版社：SERSC
摘要：An efficient implementation of discrete cosine transform (DCT) computations is presented based on the Ramanujan ordered number DCT (RDCT), a fast multiplierless DCT algorithm. Due to the simple form of the factorized matrices, the derived architecture can be easily constructed from the cascade of only two types of parameterized hardware modules: shifters and adders. The proposed implementations have many features and advantages, including low complexity, high-throughput and regularity. The regularity of RDCT algorithm and careful operation scheduling has resulted in a very efficient implementation of a multiplierless RDCT in Xilinx Spartan3 FPGA in the terms of logic requirements.
