期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：1
页码：438-443
出版社：International Journal of Soft Computing & Engineering
摘要：Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Among the reversible logic gates, Peres gate is utilized to design the multiplier since it has lower quantum cost. Operands of the multiplier is decomposed into three partitions of 8 bits each using operand decomposition method. Thus the 2424 bit reversible multiplication is performed through nine reversible 8x8 bit multipliers and output is summed to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. This proposed work is designed and developed in the VHSIC hardware description language (VHDL) code and simulation is done using Xilinx 9.1simulation tool.
关键词：Reversible logic gates; reversible logic circuits;reversible;multiplier;circuits;quantum;computing;Nanotechnology based systems.
