期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：2
页码：291-295
出版社：International Journal of Soft Computing & Engineering
摘要：In a VLSI circuit, about 70 percent of area occupies by Interconnection. Such a large number of area occupation leads to many limitations of fabricating and applying in binary circuit implementation. Multiple-valued logic is one of the most proper way to improve the ability of value and data transferring in binary systems. Nowadays as small portable devices consuming are largely increased, applying low power approaches are considerably taking into account. In this paper we suggest and evaluate a novel low power ternary full adder cell which is built with CNTFETs (Carbon Nano-Tube Field Effect Transistors). Using beneficial characteristics of CNTFET in our design and implementation notably increased the efficiency of this adder cell. Simulation results using HSPICE are reported to show that the proposed TFA (ternary full adder) consume significantly lower power and impress improvement in term of the power delay product compare to previous work.
关键词：CNTFET; Low Power;Nanoelectronic;Ternary Full Adder; Ternary Logic.
