期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：2
页码：407-413
出版社：International Journal of Soft Computing & Engineering
摘要：Cross- talk induced Delay and power consumption are two of the most important constraints in an on- chip bus design. In same metal the ratio of cross-coupling capacitance between adjacent on-chip wires is quite larger. As a consequence, cross- talk interference becomes a serious problem for VLSI design. On chip bus delay maximized by cross-talk effect when adjacent wires simultaneously switch for opposite signal transition directions. In this paper we propose a memory- based cross-talk reduction technique to minimized the cross-talk for on- chip buses based on graph representation. In this approach that represents all the illegal code words canonically generates code words efficiently. As a result, a memory-based cross-talk avoidance CODEC would need to partition large buses into small groups. Our approach is applicable for reducing the cross talk, using a unified implicit formulation. It can actually speed up the bus by exploring cross talk among neighboring wire. By using this approach, we have developed a CODEC based algorithm to minimize the cross- talk or interference in on- chip buses.
关键词：crosstalk; Bus Encoding; On-chip bus; Crosstalk;Free Algorithm; Delay.
