期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：2
页码：568-571
出版社：International Journal of Soft Computing & Engineering
摘要：An increasing part of microelectronic systems is implemented on the basis of pre designed and pre verified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of different cores. The main objective of this project is to designing a system, in such a way that; it is having the capability to detect the faults in the Read only memories. Whether the faults may be Software or Hardware, all faults can be recognized by our designed system. BIST (Built in self test) concept is introduced to detect the faults in the memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects.
