期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：4
页码：176-179
出版社：International Journal of Soft Computing & Engineering
摘要：The multi-layer advanced high-performance bus (ML-AHB) matrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB Bus Matrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. The total area and power consumption of the ML-AHB Bus Matrix of an ADK is increases due to the heavy input stages. Due to heavy input stage the cost of arbitration scheme becomes high. The computation time of each master is predictable, but it is not easy to foresee the data transfer time since the on-chip bus is usually shared by several masters. Previous works solved this issue by minimizing the latencies of several latency-critical masters, but a side effect of these methods is that they can increase the latencies of other masters; hence, they may violate the given timing constraints. It is better to apply improved Bus Matrix to some applications that do not require the time division multiple accesses to the slaves. This paper adapts improved ML-AHB Bus Matrix to multimedia applications such as a video phone, MPEG-4, and H.264 codec and presents flexible arbiter based on the Dynamic Arbitration scheme for the ML-AHB bus matrix. The arbiter supports three priority policies-fixed priority, round-robin, and dynamic priority-and three approaches to data multiplexing-transfer, transaction, and desired transfer length. Experimental results show that, although the area of the proposed Dynamic Arbitration scheme is 9%–25% larger than those of other arbitration schemes, the arbiter scheme improves the throughput by 14%–62% compared with other schemes.
关键词：Multilayer AHB (ML-AHB) bus matrix; on-chip;bus; Dynamic arbitration scheme; slave side arbitration;system-on-a-chip (SoC).
