期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：5
页码：177-179
出版社：International Journal of Soft Computing & Engineering
摘要：In this paper, an area and power efficient 128- point pipeline FFT processor is proposed for MIMO - OFDM systems based on mixed-radix 4/2 multipath delay commutator architecture (R2MDC) in terms of lower complexity and higher memory utilization. A conventional mixed radix 4/2 multipath delay commutator FFT processor will increase the hardware capacity and can be used to change the order of the input sequences. The processor is characterized with capable power-consumption for different FFT/IFFT sizes. Unlike the general mixed radix-based architectures which use a larger internal word length to achieve a high signal to noise ratio (SNR), our processor keeps the internal word length the same as the word length of the input data while adopting the block-floating point (BFP) approach to maintain the SNR. The proposed FFT processor uses different commutators which can be used to decrease the delay elements and integrate with other MIMO-OFDM processing blocks. The designed 128-point FFT processor provides 49% reduction in count of logic gates and 67% in power dissipation on 90-nm CMOS technology.
