期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2013
卷号：2
期号：6
页码：330-336
出版社：International Journal of Soft Computing & Engineering
摘要：A carry look-ahead adder improves speed by reducing the amount of time required to resolve carry bits. It is widely used in any electronic computational devices. In this paper a 4 bit & 8 bit CLA has been implemented using different static and dynamic logic styles such as Standard CMOS, DCVS Pseudo NMOS, PTL & Domino logic style. The performance of the CLA has been measured by comparing the results in terms of propagation delay, power dissipation and their Power Delay Product. The simulation is done with the help of Tanner EDA tool considering the different feature sizes of 150nm, 200nm & 250nm. Result analyses are also carried out for intrinsic and extrinsic load capacitances. This work will helpful for any circuit designer to build any system.
