期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2013
卷号：3
期号：2
页码：233-237
出版社：International Journal of Soft Computing & Engineering
摘要：The availability of increased number of resources on a single silicon chip is enforcing the designers to come up with mechanisms for efficient and effective management of these resources on a chip. Moreover defective components, chip virtualization and power-aware techniques may lead to irregular on chip interconnection topology making efficient routing a non trivial challenge. Nearly, all routing algorithms and topologies support switches that make use of routing tables for efficient routing. However memories do not scale well in terms of area and power consumption for the routing tables, thus not practical for scalable on chip networks. Logic based distributed routing (LBDR) is recently proposed as an alternative solution to the table based distributed routing which can drastically reduce the memory requirement even while being as efficient as table based distributed routing. LBDR is a simple methodology of routing that enables the removal of the routing tables at every switch and uses only a small set of bits per switch to enable efficient routing. This paper surveys different variations of efficient Logic-based distributed routing (LBDR) proposed in the NoC research literature for regular and irregular on chip interconnection topologies
