期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2013
卷号：3
期号：2
页码：347-354
出版社：International Journal of Soft Computing & Engineering
摘要：Since analog circuits have proved primarily essential in many of today’s high complex performance systems. This paper demonstrate designing and simulation of low power CMOS technology based differential amplifier at nano scale of different channel length(45nm,32nm,22nm) via applying various supply voltages i.e. 1.1V, 0.95V , 0.9V respectively. Here the high input impedance, low power dissipation circuit is mainly characterized in terms of common mode rejection ratio (CMRR), voltage gain and gain band width product .The input impedance calculated are in the range of 190 GΩ (giga ohm), cut off frequency (-3db) approximately greater than 50 MHz (mega hertz) and average power dissipation in the order of less than 130 µw (micro watt). The simulation result shows that all transistors are operated in saturation region, with this unique behavior of MOSFET transistor operating in this region not only allows a designer to work at a low voltage but also at a high frequency. Finally, the analog design consists of low operating voltages via very deep sub micron (nano scale) technology.. The simulation is carried out using PTM Low Power 45nm, 32nm, & 22nm Metal Gate / High-K / Strained-Si technology with H-spice. A Matlab tool is also used to plot the graph of various parameters at different channel length in two dimensions (2-D).
关键词：Very deep sub-micron (VDSM); Nanoelectronics;Scaling.
