期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：3
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Memory is an essential part of electronic industry. Since, the processors used in various high performance PCs, network applications and communication equipment require high speed memories. The type of memory used depends on system architecture, and its applications. This paper presents an SRAM architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are inefficient as they require idle cycles when they frequently switch between reading and writing to the memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the basis of area, speed and power
关键词：ZBT SRAM; performance analysis; READ/WRITE transitions; speed; area & power
