期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：2
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Analog-to-Digital converters are the useful component in signal processing and communication system. In the digital signal processing low power and low voltage becomes a considerable component in that are challenging for designing high speed devices and converters. This paper describes the ultra high speed ADC design with a fat tree encoder that became highly suitable and accurate. Speed becomes the important part that enhanced by component of 2 guidelines of fat tree encoder. This paper also describes the implementation of TIQ based comparator that exhibits low power consumption as compared to other comparator based design. A 3 bit ADC has been designed and simulated in CMOS 45 nm technology with input voltage range of 0 V to 0.7 V. The simulated and analysed results shows low power and a high speed performance for optimised ADC.
关键词：Fat-Tree encoder; TIQ comparator; Average power; Delay.
